kernel 5.11.14

3 files changed, 270 insertions, 36 deletions

diff --git a/SOURCES/Makefile.rhelver b/SOURCES/Makefile.rhelver
index c11ed05..8fceaba 100644
--- a/SOURCES/Makefile.rhelver
+++ b/SOURCES/Makefile.rhelver
@@ -12,7 +12,7 @@ RHEL_MINOR = 99
 #
 # Use this spot to avoid future merge conflicts.
 # Do not trim this comment.
-RHEL_RELEASE = 15
+RHEL_RELEASE = 0
 
 #
 # Early y+1 numbering
diff --git a/SOURCES/Patchlist.changelog b/SOURCES/Patchlist.changelog
index 070489e..5116d4e 100644
--- a/SOURCES/Patchlist.changelog
+++ b/SOURCES/Patchlist.changelog
@@ -1,6 +1,9 @@
 https://gitlab.com/cki-project/kernel-ark/-/commit/2632d432606c16de479f4fd0140a6ddb56ebd2dd
  2632d432606c16de479f4fd0140a6ddb56ebd2dd Re-enable PSR2 on Tigerlake with new workarounds from Intel
 
+https://gitlab.com/cki-project/kernel-ark/-/commit/06607487ea87ac1e9447fdea23a8bc9ab7c2ba49
+ 06607487ea87ac1e9447fdea23a8bc9ab7c2ba49 drm/i915/gen11+: Only load DRAM information from pcode
+
 https://gitlab.com/cki-project/kernel-ark/-/commit/6f135ea15bdf3954be0b135f4d3ca830c6582ee7
  6f135ea15bdf3954be0b135f4d3ca830c6582ee7 Fix build with patch for CVE-2021-30178
 
diff --git a/SOURCES/patch-5.11-redhat.patch b/SOURCES/patch-5.11-redhat.patch
index 197b59c..b74f557 100644
--- a/SOURCES/patch-5.11-redhat.patch
+++ b/SOURCES/patch-5.11-redhat.patch
@@ -28,10 +28,14 @@
  drivers/firmware/efi/Makefile                      |   1 +
  drivers/firmware/efi/efi.c                         | 124 +++--
  drivers/firmware/efi/secureboot.c                  |  38 ++
+ drivers/gpu/drm/i915/display/intel_bw.c            |  80 +---
  drivers/gpu/drm/i915/display/intel_dp.c            |  11 +-
  .../gpu/drm/i915/display/intel_dp_link_training.c  |  91 ++--
  .../gpu/drm/i915/display/intel_dp_link_training.h  |   2 +-
  drivers/gpu/drm/i915/display/intel_psr.c           |  14 +
+ drivers/gpu/drm/i915/i915_drv.c                    |   5 +-
+ drivers/gpu/drm/i915/i915_drv.h                    |   1 +
+ drivers/gpu/drm/i915/intel_dram.c                  |  82 +++-
  drivers/gpu/drm/panel/Kconfig                      |   9 +
  drivers/gpu/drm/panel/Makefile                     |   1 +
  drivers/gpu/drm/panel/panel-xingbangda-xbd599.c    | 366 +++++++++++++++
@@ -65,7 +69,6 @@
  security/security.c                                |   6 +
  sound/hda/Kconfig                                  |  14 +
  sound/hda/intel-dsp-config.c                       |  29 +-
- sound/soc/intel/atom/sst-mfld-platform-pcm.c       |   6 +-
  sound/soc/sof/intel/apl.c                          |   3 +-
  sound/soc/sof/intel/cnl.c                          |   3 +-
  sound/soc/sof/intel/hda-dsp.c                      |   6 +
@@ -75,7 +78,7 @@
  sound/soc/sof/ops.h                                |   8 +
  sound/soc/sof/sof-pci-dev.c                        |   2 +-
  sound/soc/sof/sof-priv.h                           |   4 +-
- 77 files changed, 2288 insertions(+), 258 deletions(-)
+ 80 files changed, 2378 insertions(+), 330 deletions(-)
 
 diff --git a/Documentation/ABI/testing/sysfs-platform_profile b/Documentation/ABI/testing/sysfs-platform_profile
 new file mode 100644
@@ -289,7 +292,7 @@ index 000000000000..c33a71263d9e
 + 2. Add the new profile name, along with a clear description of the
 +    expected behaviour, to the sysfs-platform_profile ABI documentation.
 diff --git a/Makefile b/Makefile
-index 1be83283e032..ca17261905ec 100644
+index 9116941553b8..39427f89a0cd 100644
 --- a/Makefile
 +++ b/Makefile
 @@ -495,6 +495,7 @@ KBUILD_AFLAGS   := -D__ASSEMBLY__ -fno-PIE
@@ -1110,6 +1113,123 @@ index 000000000000..de0a3714a5d4
 +		}
 +	}
 +}
+diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
+index bd060404d249..4b5a30ac84bc 100644
+--- a/drivers/gpu/drm/i915/display/intel_bw.c
++++ b/drivers/gpu/drm/i915/display/intel_bw.c
+@@ -20,76 +20,9 @@ struct intel_qgv_point {
+ struct intel_qgv_info {
+ 	struct intel_qgv_point points[I915_NUM_QGV_POINTS];
+ 	u8 num_points;
+-	u8 num_channels;
+ 	u8 t_bl;
+-	enum intel_dram_type dram_type;
+ };
+
+-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
+-					  struct intel_qgv_info *qi)
+-{
+-	u32 val = 0;
+-	int ret;
+-
+-	ret = sandybridge_pcode_read(dev_priv,
+-				     ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+-				     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
+-				     &val, NULL);
+-	if (ret)
+-		return ret;
+-
+-	if (IS_GEN(dev_priv, 12)) {
+-		switch (val & 0xf) {
+-		case 0:
+-			qi->dram_type = INTEL_DRAM_DDR4;
+-			break;
+-		case 3:
+-			qi->dram_type = INTEL_DRAM_LPDDR4;
+-			break;
+-		case 4:
+-			qi->dram_type = INTEL_DRAM_DDR3;
+-			break;
+-		case 5:
+-			qi->dram_type = INTEL_DRAM_LPDDR3;
+-			break;
+-		default:
+-			MISSING_CASE(val & 0xf);
+-			break;
+-		}
+-	} else if (IS_GEN(dev_priv, 11)) {
+-		switch (val & 0xf) {
+-		case 0:
+-			qi->dram_type = INTEL_DRAM_DDR4;
+-			break;
+-		case 1:
+-			qi->dram_type = INTEL_DRAM_DDR3;
+-			break;
+-		case 2:
+-			qi->dram_type = INTEL_DRAM_LPDDR3;
+-			break;
+-		case 3:
+-			qi->dram_type = INTEL_DRAM_LPDDR4;
+-			break;
+-		default:
+-			MISSING_CASE(val & 0xf);
+-			break;
+-		}
+-	} else {
+-		MISSING_CASE(INTEL_GEN(dev_priv));
+-		qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
+-	}
+-
+-	qi->num_channels = (val & 0xf0) >> 4;
+-	qi->num_points = (val & 0xf00) >> 8;
+-
+-	if (IS_GEN(dev_priv, 12))
+-		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
+-	else if (IS_GEN(dev_priv, 11))
+-		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
+-
+-	return 0;
+-}
+-
+ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ 					 struct intel_qgv_point *sp,
+ 					 int point)
+@@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
+ 			      struct intel_qgv_info *qi)
+ {
++	const struct dram_info *dram_info = &dev_priv->dram_info;
+ 	int i, ret;
+
+-	ret = icl_pcode_read_mem_global_info(dev_priv, qi);
+-	if (ret)
+-		return ret;
++	qi->num_points = dram_info->num_qgv_points;
++
++	if (IS_GEN(dev_priv, 12))
++		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
++	else if (IS_GEN(dev_priv, 11))
++		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
+
+ 	if (drm_WARN_ON(&dev_priv->drm,
+ 			qi->num_points > ARRAY_SIZE(qi->points)))
+@@ -209,7 +146,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
+ {
+ 	struct intel_qgv_info qi = {};
+ 	bool is_y_tile = true; /* assume y tile may be used */
+-	int num_channels;
++	int num_channels = dev_priv->dram_info.num_channels;
+ 	int deinterleave;
+ 	int ipqdepth, ipqdepthpch;
+ 	int dclk_max;
+@@ -222,7 +159,6 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
+ 			    "Failed to get memory subsystem information, ignoring bandwidth limits");
+ 		return ret;
+ 	}
+-	num_channels = qi.num_channels;
+
+ 	deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
+ 	dclk_max = icl_sagv_max_dclk(&qi);
 diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
 index 8a26307c4896..bc2aae63fe40 100644
 --- a/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1353,6 +1473,147 @@ index b3631b722de3..5089dbd240f4 100644
  	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
  		return;
 
+diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
+index 99eb0d7bbc44..85feb5742296 100644
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -609,14 +609,15 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
+ 		goto err_msi;
+
+ 	intel_opregion_setup(dev_priv);
++
++	intel_pcode_init(dev_priv);
++
+ 	/*
+ 	 * Fill the dram structure to get the system raw bandwidth and
+ 	 * dram info. This will be used for memory latency calculation.
+ 	 */
+ 	intel_dram_detect(dev_priv);
+
+-	intel_pcode_init(dev_priv);
+-
+ 	intel_bw_init_hw(dev_priv);
+
+ 	return 0;
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
+index bd5f76a28d68..a0464f73710a 100644
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -1147,6 +1147,7 @@ struct drm_i915_private {
+ 			INTEL_DRAM_LPDDR3,
+ 			INTEL_DRAM_LPDDR4
+ 		} type;
++		u8 num_qgv_points;
+ 	} dram_info;
+
+ 	struct intel_bw_info {
+diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
+index 4754296a250e..a68be91a1140 100644
+--- a/drivers/gpu/drm/i915/intel_dram.c
++++ b/drivers/gpu/drm/i915/intel_dram.c
+@@ -5,6 +5,7 @@
+
+ #include "i915_drv.h"
+ #include "intel_dram.h"
++#include "intel_sideband.h"
+
+ struct dram_dimm_info {
+ 	u16 size;
+@@ -434,6 +435,81 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
+ 	return 0;
+ }
+
++static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
++{
++	struct dram_info *dram_info = &dev_priv->dram_info;
++	u32 val = 0;
++	int ret;
++
++	ret = sandybridge_pcode_read(dev_priv,
++				     ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
++				     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
++				     &val, NULL);
++	if (ret)
++		return ret;
++
++	if (IS_GEN(dev_priv, 12)) {
++		switch (val & 0xf) {
++		case 0:
++			dram_info->type = INTEL_DRAM_DDR4;
++			break;
++		case 3:
++			dram_info->type = INTEL_DRAM_LPDDR4;
++			break;
++		case 4:
++			dram_info->type = INTEL_DRAM_DDR3;
++			break;
++		case 5:
++			dram_info->type = INTEL_DRAM_LPDDR3;
++			break;
++		default:
++			MISSING_CASE(val & 0xf);
++			return -1;
++		}
++	} else {
++		switch (val & 0xf) {
++		case 0:
++			dram_info->type = INTEL_DRAM_DDR4;
++			break;
++		case 1:
++			dram_info->type = INTEL_DRAM_DDR3;
++			break;
++		case 2:
++			dram_info->type = INTEL_DRAM_LPDDR3;
++			break;
++		case 3:
++			dram_info->type = INTEL_DRAM_LPDDR4;
++			break;
++		default:
++			MISSING_CASE(val & 0xf);
++			return -1;
++		}
++	}
++
++	dram_info->num_channels = (val & 0xf0) >> 4;
++	dram_info->num_qgv_points = (val & 0xf00) >> 8;
++
++	return 0;
++}
++
++static int gen11_get_dram_info(struct drm_i915_private *i915)
++{
++	int ret = skl_get_dram_info(i915);
++
++	if (ret)
++		return ret;
++
++	return icl_pcode_read_mem_global_info(i915);
++}
++
++static int gen12_get_dram_info(struct drm_i915_private *i915)
++{
++	/* Always needed for GEN12+ */
++	i915->dram_info.is_16gb_dimm = true;
++
++	return icl_pcode_read_mem_global_info(i915);
++}
++
+ void intel_dram_detect(struct drm_i915_private *i915)
+ {
+ 	struct dram_info *dram_info = &i915->dram_info;
+@@ -449,7 +525,11 @@ void intel_dram_detect(struct drm_i915_private *i915)
+ 	if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
+ 		return;
+
+-	if (IS_GEN9_LP(i915))
++	if (INTEL_GEN(i915) >= 12)
++		ret = gen12_get_dram_info(i915);
++	else if (INTEL_GEN(i915) >= 11)
++		ret = gen11_get_dram_info(i915);
++	else if (IS_GEN9_LP(i915))
+ 		ret = bxt_get_dram_info(i915);
+ 	else
+ 		ret = skl_get_dram_info(i915);
 diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
 index b4e021ea30f9..5687b745ebe2 100644
 --- a/drivers/gpu/drm/panel/Kconfig
@@ -3790,36 +4051,6 @@ index c45686172517..68bb977c6a37 100644
  		.acpi_hid = "808622A8",
  	},
  #endif
-diff --git a/sound/soc/intel/atom/sst-mfld-platform-pcm.c b/sound/soc/intel/atom/sst-mfld-platform-pcm.c
-index 9e9b05883557..aa5dd590ddd5 100644
---- a/sound/soc/intel/atom/sst-mfld-platform-pcm.c
-+++ b/sound/soc/intel/atom/sst-mfld-platform-pcm.c
-@@ -488,14 +488,14 @@ static struct snd_soc_dai_driver sst_platform_dai[] = {
- 		.channels_min = SST_STEREO,
- 		.channels_max = SST_STEREO,
- 		.rates = SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000,
--		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
- 	},
- 	.capture = {
- 		.stream_name = "Headset Capture",
- 		.channels_min = 1,
- 		.channels_max = 2,
- 		.rates = SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000,
--		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
- 	},
- },
- {
-@@ -506,7 +506,7 @@ static struct snd_soc_dai_driver sst_platform_dai[] = {
- 		.channels_min = SST_STEREO,
- 		.channels_max = SST_STEREO,
- 		.rates = SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000,
--		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
- 	},
- },
- {
 diff --git a/sound/soc/sof/intel/apl.c b/sound/soc/sof/intel/apl.c
 index fc29b91b8932..c7ed2b3d6abc 100644
 --- a/sound/soc/sof/intel/apl.c
@@ -3853,10 +4084,10 @@ index e38db519f38d..094cde17a1b7 100644
  	/* Register IO */
  	.write		= sof_io_write,
 diff --git a/sound/soc/sof/intel/hda-dsp.c b/sound/soc/sof/intel/hda-dsp.c
-index 012bac41fee0..03b0f178ca08 100644
+index ea8e7ad8684d..d87cc16d53f6 100644
 --- a/sound/soc/sof/intel/hda-dsp.c
 +++ b/sound/soc/sof/intel/hda-dsp.c
-@@ -885,6 +885,12 @@ int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
+@@ -892,6 +892,12 @@ int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
  	return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
  }