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author | Jan200101 <sentrycraft123@gmail.com> | 2022-09-25 02:03:17 +0200 |
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committer | Jan200101 <sentrycraft123@gmail.com> | 2022-09-25 02:03:17 +0200 |
commit | 264c64fc1ac744ed6bc0f8d38c208c4afb8b8d94 (patch) | |
tree | a6ce6a5066584a101383758674ddf3828242e108 /SOURCES/revert-iommu-recursive-locking.patch | |
parent | 5579eb45e00fd53dfe6a48bbadabc6c994b83464 (diff) | |
download | kernel-fsync-264c64fc1ac744ed6bc0f8d38c208c4afb8b8d94.tar.gz kernel-fsync-264c64fc1ac744ed6bc0f8d38c208c4afb8b8d94.zip |
kernel 5.19.10
Diffstat (limited to 'SOURCES/revert-iommu-recursive-locking.patch')
-rw-r--r-- | SOURCES/revert-iommu-recursive-locking.patch | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/SOURCES/revert-iommu-recursive-locking.patch b/SOURCES/revert-iommu-recursive-locking.patch new file mode 100644 index 0000000..3244352 --- /dev/null +++ b/SOURCES/revert-iommu-recursive-locking.patch @@ -0,0 +1,139 @@ +--- + include/linux/dmar.h | 4 +--- + drivers/iommu/intel/dmar.c | 7 ------- + drivers/iommu/intel/iommu.c | 27 +++++++++++++++++++++++++-- + 3 files changed, 26 insertions(+), 12 deletions(-) + +diff --git a/include/linux/dmar.h b/include/linux/dmar.h +index 8917a32173c4..d81a51978d01 100644 +--- a/include/linux/dmar.h ++++ b/include/linux/dmar.h +@@ -65,7 +65,6 @@ struct dmar_pci_notify_info { + + extern struct rw_semaphore dmar_global_lock; + extern struct list_head dmar_drhd_units; +-extern int intel_iommu_enabled; + + #define for_each_drhd_unit(drhd) \ + list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ +@@ -89,8 +88,7 @@ extern int intel_iommu_enabled; + static inline bool dmar_rcu_check(void) + { + return rwsem_is_locked(&dmar_global_lock) || +- system_state == SYSTEM_BOOTING || +- (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled); ++ system_state == SYSTEM_BOOTING; + } + + #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) +diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c +index 04f7991734a9..3528058d253e 100644 +--- a/drivers/iommu/intel/dmar.c ++++ b/drivers/iommu/intel/dmar.c +@@ -2356,13 +2356,6 @@ static int dmar_device_hotplug(acpi_handle handle, bool insert) + if (!dmar_in_use()) + return 0; + +- /* +- * It's unlikely that any I/O board is hot added before the IOMMU +- * subsystem is initialized. +- */ +- if (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled) +- return -EOPNOTSUPP; +- + if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { + tmp = handle; + } else { +diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c +index c20f3e060bac..5bab71a05830 100644 +--- a/drivers/iommu/intel/iommu.c ++++ b/drivers/iommu/intel/iommu.c +@@ -3029,7 +3029,13 @@ static int __init init_dmars(void) + + #ifdef CONFIG_INTEL_IOMMU_SVM + if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { ++ /* ++ * Call dmar_alloc_hwirq() with dmar_global_lock held, ++ * could cause possible lock race condition. ++ */ ++ up_write(&dmar_global_lock); + ret = intel_svm_enable_prq(iommu); ++ down_write(&dmar_global_lock); + if (ret) + goto free_iommu; + } +@@ -3941,6 +3947,7 @@ int __init intel_iommu_init(void) + force_on = (!intel_iommu_tboot_noforce && tboot_force_iommu()) || + platform_optin_force_iommu(); + ++ down_write(&dmar_global_lock); + if (dmar_table_init()) { + if (force_on) + panic("tboot: Failed to initialize DMAR table\n"); +@@ -3953,6 +3960,16 @@ int __init intel_iommu_init(void) + goto out_free_dmar; + } + ++ up_write(&dmar_global_lock); ++ ++ /* ++ * The bus notifier takes the dmar_global_lock, so lockdep will ++ * complain later when we register it under the lock. ++ */ ++ dmar_register_bus_notifier(); ++ ++ down_write(&dmar_global_lock); ++ + if (!no_iommu) + intel_iommu_debugfs_init(); + +@@ -3997,9 +4014,11 @@ int __init intel_iommu_init(void) + pr_err("Initialization failed\n"); + goto out_free_dmar; + } ++ up_write(&dmar_global_lock); + + init_iommu_pm_ops(); + ++ down_read(&dmar_global_lock); + for_each_active_iommu(iommu, drhd) { + /* + * The flush queue implementation does not perform +@@ -4137,11 +4137,13 @@ + "%s", iommu->name); + iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); + } ++ up_read(&dmar_global_lock); + + bus_set_iommu(&pci_bus_type, &intel_iommu_ops); + if (si_domain && !hw_pass_through) + register_memory_notifier(&intel_iommu_memory_nb); + ++ down_read(&dmar_global_lock); + if (probe_acpi_namespace_devices()) + pr_warn("ACPI name space devices didn't probe correctly\n"); + +@@ -4031,15 +4052,17 @@ int __init intel_iommu_init(void) + + iommu_disable_protect_mem_regions(iommu); + } ++ up_read(&dmar_global_lock); + +- intel_iommu_enabled = 1; +- dmar_register_bus_notifier(); + pr_info("Intel(R) Virtualization Technology for Directed I/O\n"); + ++ intel_iommu_enabled = 1; ++ + return 0; + + out_free_dmar: + intel_iommu_free_dmars(); ++ up_write(&dmar_global_lock); + return ret; + } + +-- +2.34.1 + +
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