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-rw-r--r--SOURCES/arm64-tegra-enable-dfll-on-jetson-nano.patch86
1 files changed, 86 insertions, 0 deletions
diff --git a/SOURCES/arm64-tegra-enable-dfll-on-jetson-nano.patch b/SOURCES/arm64-tegra-enable-dfll-on-jetson-nano.patch
new file mode 100644
index 0000000..8add84f
--- /dev/null
+++ b/SOURCES/arm64-tegra-enable-dfll-on-jetson-nano.patch
@@ -0,0 +1,86 @@
+From 72fd21b62055b985d3e3fb72a1e70e3d09596174 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Sun, 27 Sep 2020 18:20:41 +0100
+Subject: [PATCH] arm64: tegra: Enable DFLL support on Jetson Nano
+
+Populate the DFLL node and corresponding PWM pin nodes in order to
+enable CPUFREQ support on the Jetson Nano platform.
+
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+---
+ .../boot/dts/nvidia/tegra210-p3450-0000.dts | 50 +++++++++++++++----
+ 1 file changed, 40 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+index 9bc52fdb393c..4d980d753a98 100644
+--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
++++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+@@ -101,6 +101,22 @@ gpu@57000000 {
+ status = "okay";
+ };
+
++ pinmux@700008d4 {
++ dvfs_pwm_active_state: dvfs_pwm_active {
++ dvfs_pwm_pbb1 {
++ nvidia,pins = "dvfs_pwm_pbb1";
++ nvidia,tristate = <TEGRA_PIN_DISABLE>;
++ };
++ };
++
++ dvfs_pwm_inactive_state: dvfs_pwm_inactive {
++ dvfs_pwm_pbb1 {
++ nvidia,pins = "dvfs_pwm_pbb1";
++ nvidia,tristate = <TEGRA_PIN_ENABLE>;
++ };
++ };
++ };
++
+ /* debug port */
+ serial@70006000 {
+ status = "okay";
+@@ -574,17 +590,31 @@ sdhci@700b0400 {
+ wakeup-source;
+ };
+
+- clocks {
+- compatible = "simple-bus";
+- #address-cells = <1>;
+- #size-cells = <0>;
++ clock@70110000 {
++ status = "okay";
+
+- clk32k_in: clock@0 {
+- compatible = "fixed-clock";
+- reg = <0>;
+- #clock-cells = <0>;
+- clock-frequency = <32768>;
+- };
++ nvidia,cf = <6>;
++ nvidia,ci = <0>;
++ nvidia,cg = <2>;
++ nvidia,droop-ctrl = <0x00000f00>;
++ nvidia,force-mode = <1>;
++ nvidia,sample-rate = <25000>;
++
++ nvidia,pwm-min-microvolts = <708000>;
++ nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
++ nvidia,pwm-to-pmic;
++ nvidia,pwm-tristate-microvolts = <1000000>;
++ nvidia,pwm-voltage-step-microvolts = <19200>;
++
++ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
++ pinctrl-0 = <&dvfs_pwm_active_state>;
++ pinctrl-1 = <&dvfs_pwm_inactive_state>;
++ };
++
++ clk32k_in: clock@0 {
++ compatible = "fixed-clock";
++ clock-frequency = <32768>;
++ #clock-cells = <0>;
+ };
+
+ cpus {
+--
+2.26.2
+