From 3ea603c82a3b7b5d45f21e35d8ce9f6029ff6c3a Mon Sep 17 00:00:00 2001
From: joachimschmidt557 <joachim.schmidt557@outlook.com>
Date: Mon, 7 Mar 2022 19:33:58 +0100
Subject: stage2 ARM: implement ptr_add, ptr_sub for all element sizes

Also reduces slice_elem_val to ptr_add, simplifying the implementation
---
 test/behavior/array.zig | 1 -
 1 file changed, 1 deletion(-)

(limited to 'test/behavior/array.zig')

diff --git a/test/behavior/array.zig b/test/behavior/array.zig
index 6482c1db2d..e6204729d4 100644
--- a/test/behavior/array.zig
+++ b/test/behavior/array.zig
@@ -8,7 +8,6 @@ const expectEqual = testing.expectEqual;
 test "array to slice" {
     if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
 
     const a: u32 align(4) = 3;
     const b: u32 align(8) = 4;
-- 
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