From a3854d042e0d05a87ae9f0b71d12474c8d0e57ec Mon Sep 17 00:00:00 2001
From: Andrew Kelley <andrew@ziglang.org>
Date: Thu, 18 Jul 2019 15:03:21 -0400
Subject: basic riscv support

llvm is giving me `error: couldn't allocate output register for
constraint '{a0}'` which is a bug that needs to be fixed upstream.
---
 std/os/bits/linux.zig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'std/os/bits/linux.zig')

diff --git a/std/os/bits/linux.zig b/std/os/bits/linux.zig
index 8430a05bf0..d7c23ffadb 100644
--- a/std/os/bits/linux.zig
+++ b/std/os/bits/linux.zig
@@ -7,6 +7,7 @@ pub usingnamespace @import("linux/errno.zig");
 pub usingnamespace switch (builtin.arch) {
     .x86_64 => @import("linux/x86_64.zig"),
     .aarch64 => @import("linux/arm64.zig"),
+    .riscv64 => @import("linux/riscv64.zig"),
     else => struct {},
 };
 
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