From 138afd5cbfbe17829082efa3084f63de88aa1c90 Mon Sep 17 00:00:00 2001
From: Andrew Kelley <andrew@ziglang.org>
Date: Thu, 10 Jun 2021 20:13:43 -0700
Subject: zig fmt

---
 src/codegen/spirv.zig | 15 ++++++---------
 src/link/MachO.zig    |  2 +-
 src/link/SpirV.zig    |  5 +----
 3 files changed, 8 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/src/codegen/spirv.zig b/src/codegen/spirv.zig
index 4ce5de7523..3bff09bd8d 100644
--- a/src/codegen/spirv.zig
+++ b/src/codegen/spirv.zig
@@ -885,10 +885,7 @@ pub const DeclGen = struct {
         if (inst.operand.ty.hasCodeGenBits()) {
             const operand_id = try self.resolve(inst.operand);
             // current_block_label_id should not be undefined here, lest there is a br or br_void in the function's body.
-            try target.incoming_blocks.append(self.spv.gpa, .{
-                .src_label_id = self.current_block_label_id,
-                .break_value_id = operand_id
-            });
+            try target.incoming_blocks.append(self.spv.gpa, .{ .src_label_id = self.current_block_label_id, .break_value_id = operand_id });
         }
 
         try writeInstruction(&self.code, .OpBranch, &[_]Word{target.label_id});
@@ -936,9 +933,9 @@ pub const DeclGen = struct {
         const result_id = self.spv.allocResultId();
 
         const operands = if (inst.base.ty.isVolatilePtr())
-            &[_]Word{ result_type_id, result_id, operand_id, @bitCast(u32, spec.MemoryAccess{.Volatile = true}) }
+            &[_]Word{ result_type_id, result_id, operand_id, @bitCast(u32, spec.MemoryAccess{ .Volatile = true }) }
         else
-            &[_]Word{ result_type_id, result_id, operand_id};
+            &[_]Word{ result_type_id, result_id, operand_id };
 
         try writeInstruction(&self.code, .OpLoad, operands);
 
@@ -950,14 +947,14 @@ pub const DeclGen = struct {
         const loop_label_id = self.spv.allocResultId();
 
         // Jump to the loop entry point
-        try writeInstruction(&self.code, .OpBranch, &[_]Word{ loop_label_id });
+        try writeInstruction(&self.code, .OpBranch, &[_]Word{loop_label_id});
 
         // TODO: Look into OpLoopMerge.
 
         try self.beginSPIRVBlock(loop_label_id);
         try self.genBody(inst.body);
 
-        try writeInstruction(&self.code, .OpBranch, &[_]Word{ loop_label_id });
+        try writeInstruction(&self.code, .OpBranch, &[_]Word{loop_label_id});
     }
 
     fn genRet(self: *DeclGen, inst: *Inst.UnOp) !void {
@@ -976,7 +973,7 @@ pub const DeclGen = struct {
         const src_val_id = try self.resolve(inst.rhs);
 
         const operands = if (inst.lhs.ty.isVolatilePtr())
-            &[_]Word{ dst_ptr_id, src_val_id, @bitCast(u32, spec.MemoryAccess{.Volatile = true}) }
+            &[_]Word{ dst_ptr_id, src_val_id, @bitCast(u32, spec.MemoryAccess{ .Volatile = true }) }
         else
             &[_]Word{ dst_ptr_id, src_val_id };
 
diff --git a/src/link/MachO.zig b/src/link/MachO.zig
index d4d7de15e4..24dfa2c328 100644
--- a/src/link/MachO.zig
+++ b/src/link/MachO.zig
@@ -2517,7 +2517,7 @@ fn allocatedSizeLinkedit(self: *MachO, start: u64) u64 {
 
     return min_pos - start;
 }
-fn checkForCollision(start: u64, end: u64, off: u64, size: u64) callconv(.Inline) ?u64 {
+inline fn checkForCollision(start: u64, end: u64, off: u64, size: u64) ?u64 {
     const increased_size = padToIdeal(size);
     const test_end = off + increased_size;
     if (end > off and start < test_end) {
diff --git a/src/link/SpirV.zig b/src/link/SpirV.zig
index f80e4aec01..9d64245bbb 100644
--- a/src/link/SpirV.zig
+++ b/src/link/SpirV.zig
@@ -187,10 +187,7 @@ pub fn flushModule(self: *SpirV, comp: *Compilation) !void {
     var iovc_buffers: [buffers.len]std.os.iovec_const = undefined;
     for (iovc_buffers) |*iovc, i| {
         const bytes = std.mem.sliceAsBytes(buffers[i]);
-        iovc.* = .{
-            .iov_base = bytes.ptr,
-            .iov_len = bytes.len
-        };
+        iovc.* = .{ .iov_base = bytes.ptr, .iov_len = bytes.len };
     }
 
     var file_size: u64 = 0;
-- 
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