From d99437917363d0b550af5e20360bd07bc98367ba Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Tue, 16 Jul 2019 19:54:14 -0400 Subject: update bundled musl source to 1.1.23 --- src/target.cpp | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) (limited to 'src/target.cpp') diff --git a/src/target.cpp b/src/target.cpp index 56c9a72c8f..e5226bd520 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -1524,7 +1524,7 @@ static const AvailableLibC libcs_available[] = { {ZigLLVM_aarch64_be, OsLinux, ZigLLVM_Musl}, {ZigLLVM_aarch64_be, OsWindows, ZigLLVM_GNU}, {ZigLLVM_aarch64, OsLinux, ZigLLVM_GNU}, - {ZigLLVM_aarch64, OsLinux, ZigLLVM_MuslEABI}, + {ZigLLVM_aarch64, OsLinux, ZigLLVM_Musl}, {ZigLLVM_aarch64, OsWindows, ZigLLVM_GNU}, {ZigLLVM_armeb, OsLinux, ZigLLVM_GNUEABI}, {ZigLLVM_armeb, OsLinux, ZigLLVM_GNUEABIHF}, @@ -1555,7 +1555,6 @@ static const AvailableLibC libcs_available[] = { {ZigLLVM_ppc64, OsLinux, ZigLLVM_Musl}, {ZigLLVM_ppc, OsLinux, ZigLLVM_GNU}, {ZigLLVM_ppc, OsLinux, ZigLLVM_Musl}, - {ZigLLVM_riscv32, OsLinux, ZigLLVM_Musl}, {ZigLLVM_riscv64, OsLinux, ZigLLVM_GNU}, {ZigLLVM_riscv64, OsLinux, ZigLLVM_Musl}, {ZigLLVM_systemz, OsLinux, ZigLLVM_GNU}, @@ -1655,3 +1654,36 @@ void target_libc_enum(size_t index, ZigTarget *out_target) { bool target_has_debug_info(const ZigTarget *target) { return !target_is_wasm(target); } + +const char *target_arch_musl_name(ZigLLVM_ArchType arch) { + switch (arch) { + case ZigLLVM_aarch64: + case ZigLLVM_aarch64_be: + return "aarch64"; + case ZigLLVM_arm: + case ZigLLVM_armeb: + return "arm"; + case ZigLLVM_mips: + case ZigLLVM_mipsel: + return "mips"; + case ZigLLVM_mips64el: + case ZigLLVM_mips64: + return "mips64"; + case ZigLLVM_ppc: + return "powerpc"; + case ZigLLVM_ppc64: + case ZigLLVM_ppc64le: + return "powerpc64"; + case ZigLLVM_systemz: + return "s390x"; + case ZigLLVM_x86: + return "i386"; + case ZigLLVM_x86_64: + return "x86_64"; + case ZigLLVM_riscv64: + return "riscv64"; + default: + zig_unreachable(); + } +} + -- cgit v1.2.3 From c0b4121ff2d31b2ef37e480eec18f0bd063d7a2d Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Tue, 16 Jul 2019 21:38:18 -0400 Subject: libc headers before C language headers, and disable libunwind on arm32 --- src/codegen.cpp | 7 ++++--- src/link.cpp | 8 ++++++-- src/target.cpp | 6 ++++++ src/target.hpp | 1 + 4 files changed, 17 insertions(+), 5 deletions(-) (limited to 'src/target.cpp') diff --git a/src/codegen.cpp b/src/codegen.cpp index fbf6c98f12..188c5ccc8d 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -8390,15 +8390,16 @@ void add_cc_args(CodeGen *g, ZigList &args, const char *out_dep_pa } } - args.append("-isystem"); - args.append(buf_ptr(g->zig_c_headers_dir)); - for (size_t i = 0; i < g->libc_include_dir_len; i += 1) { Buf *include_dir = g->libc_include_dir_list[i]; args.append("-isystem"); args.append(buf_ptr(include_dir)); } + // According to Rich Felker libc headers are supposed to go before C language headers. + args.append("-isystem"); + args.append(buf_ptr(g->zig_c_headers_dir)); + if (g->zig_target->is_native) { args.append("-march=native"); } else { diff --git a/src/link.cpp b/src/link.cpp index 4d2144f5cc..44b3abaa90 100644 --- a/src/link.cpp +++ b/src/link.cpp @@ -1775,11 +1775,15 @@ static void construct_linker_job_elf(LinkJob *lj) { lj->args.append("--no-as-needed"); } } else if (target_is_glibc(g->zig_target)) { - lj->args.append(build_libunwind(g)); + if (target_supports_libunwind(g->zig_target)) { + lj->args.append(build_libunwind(g)); + } add_glibc_libs(lj); lj->args.append(get_libc_crt_file(g, "libc_nonshared.a")); } else if (target_is_musl(g->zig_target)) { - lj->args.append(build_libunwind(g)); + if (target_supports_libunwind(g->zig_target)) { + lj->args.append(build_libunwind(g)); + } lj->args.append(build_musl(g)); } else { zig_unreachable(); diff --git a/src/target.cpp b/src/target.cpp index e5226bd520..804c421618 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -1687,3 +1687,9 @@ const char *target_arch_musl_name(ZigLLVM_ArchType arch) { } } +bool target_supports_libunwind(const ZigTarget *target) { + if (target->arch == ZigLLVM_arm || target->arch == ZigLLVM_armeb) { + return false; + } + return true; +} diff --git a/src/target.hpp b/src/target.hpp index 483172cc94..fcda9955b9 100644 --- a/src/target.hpp +++ b/src/target.hpp @@ -189,6 +189,7 @@ bool target_is_single_threaded(const ZigTarget *target); bool target_supports_stack_probing(const ZigTarget *target); bool target_has_debug_info(const ZigTarget *target); const char *target_arch_musl_name(ZigLLVM_ArchType arch); +bool target_supports_libunwind(const ZigTarget *target); uint32_t target_arch_pointer_bit_width(ZigLLVM_ArchType arch); -- cgit v1.2.3 From 95e04e3874dd1284c39182e7909d122ceb1c56c4 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Wed, 17 Jul 2019 12:40:48 -0400 Subject: back to msvc as the default C ABI on Windows Zig provides a libc for the GNU C ABI on Windows, and cannot (at least yet) provide one for the MSVC C ABI. However when not linking libc, zig has no problem targeting MSVC as the C ABI. And this should be the default. Related: #2911 --- src/target.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/target.cpp') diff --git a/src/target.cpp b/src/target.cpp index 804c421618..6a949270ae 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -1477,9 +1477,9 @@ ZigLLVM_EnvironmentType target_default_abi(ZigLLVM_ArchType arch, Os os) { case OsKFreeBSD: case OsNetBSD: case OsHurd: - case OsWindows: return ZigLLVM_GNU; case OsUefi: + case OsWindows: return ZigLLVM_MSVC; case OsLinux: case OsWASI: -- cgit v1.2.3 From 38b5812c4895eb0157f99348f51c40bbd17c3b94 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Thu, 1 Aug 2019 02:37:22 -0400 Subject: allow 128 bit cmpxchg on x86_64 --- src/ir.cpp | 7 +++-- src/target.cpp | 66 ++++++++++++++++++++++++++++++++++++++++ src/target.hpp | 1 + test/stage1/behavior/atomics.zig | 20 ++++++++++++ 4 files changed, 91 insertions(+), 3 deletions(-) (limited to 'src/target.cpp') diff --git a/src/ir.cpp b/src/ir.cpp index be7a8e2e51..f34c840496 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -24735,10 +24735,11 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstruction *op operand_type->data.integral.bit_count)); return ira->codegen->builtin_types.entry_invalid; } - if (operand_type->data.integral.bit_count > ira->codegen->pointer_size_bytes * 8) { + uint32_t max_atomic_bits = target_arch_largest_atomic_bits(ira->codegen->zig_target->arch); + if (operand_type->data.integral.bit_count > max_atomic_bits) { ir_add_error(ira, op, - buf_sprintf("expected integer type pointer size or smaller, found %" PRIu32 "-bit integer type", - operand_type->data.integral.bit_count)); + buf_sprintf("expected %" PRIu32 "-bit integer type or smaller, found %" PRIu32 "-bit integer type", + max_atomic_bits, operand_type->data.integral.bit_count)); return ira->codegen->builtin_types.entry_invalid; } if (!is_power_of_2(operand_type->data.integral.bit_count)) { diff --git a/src/target.cpp b/src/target.cpp index 6a949270ae..7bb248a35f 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -863,6 +863,71 @@ uint32_t target_arch_pointer_bit_width(ZigLLVM_ArchType arch) { zig_unreachable(); } +uint32_t target_arch_largest_atomic_bits(ZigLLVM_ArchType arch) { + switch (arch) { + case ZigLLVM_UnknownArch: + zig_unreachable(); + + case ZigLLVM_avr: + case ZigLLVM_msp430: + return 16; + + case ZigLLVM_arc: + case ZigLLVM_arm: + case ZigLLVM_armeb: + case ZigLLVM_hexagon: + case ZigLLVM_le32: + case ZigLLVM_mips: + case ZigLLVM_mipsel: + case ZigLLVM_nvptx: + case ZigLLVM_ppc: + case ZigLLVM_r600: + case ZigLLVM_riscv32: + case ZigLLVM_sparc: + case ZigLLVM_sparcel: + case ZigLLVM_tce: + case ZigLLVM_tcele: + case ZigLLVM_thumb: + case ZigLLVM_thumbeb: + case ZigLLVM_x86: + case ZigLLVM_xcore: + case ZigLLVM_amdil: + case ZigLLVM_hsail: + case ZigLLVM_spir: + case ZigLLVM_kalimba: + case ZigLLVM_lanai: + case ZigLLVM_shave: + case ZigLLVM_wasm32: + case ZigLLVM_renderscript32: + return 32; + + case ZigLLVM_aarch64: + case ZigLLVM_aarch64_be: + case ZigLLVM_amdgcn: + case ZigLLVM_bpfel: + case ZigLLVM_bpfeb: + case ZigLLVM_le64: + case ZigLLVM_mips64: + case ZigLLVM_mips64el: + case ZigLLVM_nvptx64: + case ZigLLVM_ppc64: + case ZigLLVM_ppc64le: + case ZigLLVM_riscv64: + case ZigLLVM_sparcv9: + case ZigLLVM_systemz: + case ZigLLVM_amdil64: + case ZigLLVM_hsail64: + case ZigLLVM_spir64: + case ZigLLVM_wasm64: + case ZigLLVM_renderscript64: + return 64; + + case ZigLLVM_x86_64: + return 128; + } + zig_unreachable(); +} + uint32_t target_c_type_size_in_bits(const ZigTarget *target, CIntType id) { switch (target->os) { case OsFreestanding: @@ -1693,3 +1758,4 @@ bool target_supports_libunwind(const ZigTarget *target) { } return true; } + diff --git a/src/target.hpp b/src/target.hpp index fcda9955b9..985a4c11b4 100644 --- a/src/target.hpp +++ b/src/target.hpp @@ -192,6 +192,7 @@ const char *target_arch_musl_name(ZigLLVM_ArchType arch); bool target_supports_libunwind(const ZigTarget *target); uint32_t target_arch_pointer_bit_width(ZigLLVM_ArchType arch); +uint32_t target_arch_largest_atomic_bits(ZigLLVM_ArchType arch); size_t target_libc_count(void); void target_libc_enum(size_t index, ZigTarget *out_target); diff --git a/test/stage1/behavior/atomics.zig b/test/stage1/behavior/atomics.zig index daa463fd45..3d1caaaa15 100644 --- a/test/stage1/behavior/atomics.zig +++ b/test/stage1/behavior/atomics.zig @@ -69,3 +69,23 @@ test "cmpxchg with ptr" { expect(@cmpxchgStrong(*i32, &x, &data3, &data2, AtomicOrder.SeqCst, AtomicOrder.SeqCst) == null); expect(x == &data2); } + +test "128-bit cmpxchg" { + if (builtin.arch != .x86_64) { + return error.SkipZigTest; + } + var x: u128 align(16) = 1234; // TODO: https://github.com/ziglang/zig/issues/2987 + if (@cmpxchgWeak(u128, &x, 99, 5678, .SeqCst, .SeqCst)) |x1| { + expect(x1 == 1234); + } else { + @panic("cmpxchg should have failed"); + } + + while (@cmpxchgWeak(u128, &x, 1234, 5678, .SeqCst, .SeqCst)) |x1| { + expect(x1 == 1234); + } + expect(x == 5678); + + expect(@cmpxchgStrong(u128, &x, 5678, 42, .SeqCst, .SeqCst) == null); + expect(x == 42); +} -- cgit v1.2.3 From 24d5ec078355d68e3f1002220fd284b1ff02a465 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Sun, 11 Aug 2019 22:35:12 -0400 Subject: fix async function frames not aligned enough --- src/analyze.cpp | 10 ++++----- src/analyze.hpp | 2 +- src/target.cpp | 4 ++++ src/target.hpp | 2 ++ std/event/channel.zig | 62 +++++++++++++++++++++++---------------------------- 5 files changed, 40 insertions(+), 40 deletions(-) (limited to 'src/target.cpp') diff --git a/src/analyze.cpp b/src/analyze.cpp index 30aa82a216..9cd3ba026b 100644 --- a/src/analyze.cpp +++ b/src/analyze.cpp @@ -1500,7 +1500,7 @@ bool type_is_invalid(ZigType *type_entry) { ZigType *get_struct_type(CodeGen *g, const char *type_name, const char *field_names[], - ZigType *field_types[], size_t field_count) + ZigType *field_types[], size_t field_count, unsigned min_abi_align) { ZigType *struct_type = new_type_table_entry(ZigTypeIdStruct); @@ -1512,7 +1512,7 @@ ZigType *get_struct_type(CodeGen *g, const char *type_name, const char *field_na struct_type->data.structure.fields = allocate(field_count); struct_type->data.structure.fields_by_name.init(field_count); - size_t abi_align = 0; + size_t abi_align = min_abi_align; for (size_t i = 0; i < field_count; i += 1) { TypeStructField *field = &struct_type->data.structure.fields[i]; field->name = buf_create_from_str(field_names[i]); @@ -5334,7 +5334,7 @@ static Error resolve_coro_frame(CodeGen *g, ZigType *frame_type) { assert(field_names.length == field_types.length); frame_type->data.frame.locals_struct = get_struct_type(g, buf_ptr(&frame_type->name), - field_names.items, field_types.items, field_names.length); + field_names.items, field_types.items, field_names.length, target_fn_align(g->zig_target)); frame_type->abi_size = frame_type->data.frame.locals_struct->abi_size; frame_type->abi_align = frame_type->data.frame.locals_struct->abi_align; frame_type->size_in_bits = frame_type->data.frame.locals_struct->size_in_bits; @@ -7764,8 +7764,8 @@ static void resolve_llvm_types(CodeGen *g, ZigType *type, ResolveStatus wanted_r LLVMTypeRef get_llvm_type(CodeGen *g, ZigType *type) { assertNoError(type_resolve(g, type, ResolveStatusLLVMFull)); - assert(type->abi_size == 0 || type->abi_size == LLVMABISizeOfType(g->target_data_ref, type->llvm_type)); - assert(type->abi_align == 0 || type->abi_align == LLVMABIAlignmentOfType(g->target_data_ref, type->llvm_type)); + assert(type->abi_size == 0 || type->abi_size >= LLVMABISizeOfType(g->target_data_ref, type->llvm_type)); + assert(type->abi_align == 0 || type->abi_align >= LLVMABIAlignmentOfType(g->target_data_ref, type->llvm_type)); return type->llvm_type; } diff --git a/src/analyze.hpp b/src/analyze.hpp index 3115c79b40..97d8de7bb1 100644 --- a/src/analyze.hpp +++ b/src/analyze.hpp @@ -39,7 +39,7 @@ ZigType *get_error_union_type(CodeGen *g, ZigType *err_set_type, ZigType *payloa ZigType *get_bound_fn_type(CodeGen *g, ZigFn *fn_entry); ZigType *get_opaque_type(CodeGen *g, Scope *scope, AstNode *source_node, const char *full_name, Buf *bare_name); ZigType *get_struct_type(CodeGen *g, const char *type_name, const char *field_names[], - ZigType *field_types[], size_t field_count); + ZigType *field_types[], size_t field_count, unsigned min_abi_align); ZigType *get_test_fn_type(CodeGen *g); ZigType *get_any_frame_type(CodeGen *g, ZigType *result_type); bool handle_is_ptr(ZigType *type_entry); diff --git a/src/target.cpp b/src/target.cpp index 7bb248a35f..d1ae64acd4 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -1759,3 +1759,7 @@ bool target_supports_libunwind(const ZigTarget *target) { return true; } + +unsigned target_fn_align(const ZigTarget *target) { + return 16; +} diff --git a/src/target.hpp b/src/target.hpp index 985a4c11b4..cc8da97777 100644 --- a/src/target.hpp +++ b/src/target.hpp @@ -197,4 +197,6 @@ uint32_t target_arch_largest_atomic_bits(ZigLLVM_ArchType arch); size_t target_libc_count(void); void target_libc_enum(size_t index, ZigTarget *out_target); +unsigned target_fn_align(const ZigTarget *target); + #endif diff --git a/std/event/channel.zig b/std/event/channel.zig index c4f7dca085..fa5ad6575f 100644 --- a/std/event/channel.zig +++ b/std/event/channel.zig @@ -2,8 +2,6 @@ const std = @import("../std.zig"); const builtin = @import("builtin"); const assert = std.debug.assert; const testing = std.testing; -const AtomicRmwOp = builtin.AtomicRmwOp; -const AtomicOrder = builtin.AtomicOrder; const Loop = std.event.Loop; /// many producer, many consumer, thread-safe, runtime configurable buffer size @@ -98,18 +96,18 @@ pub fn Channel(comptime T: type) type { // TODO test canceling a put() errdefer { - _ = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.put_count, .Sub, 1, .SeqCst); const need_dispatch = !self.putters.remove(&queue_node); self.loop.cancelOnNextTick(&my_tick_node); if (need_dispatch) { // oops we made the put_count incorrect for a period of time. fix by dispatching. - _ = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.put_count, .Add, 1, .SeqCst); self.dispatch(); } } suspend { self.putters.put(&queue_node); - _ = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.put_count, .Add, 1, .SeqCst); self.dispatch(); } @@ -118,8 +116,7 @@ pub fn Channel(comptime T: type) type { /// await this function to get an item from the channel. If the buffer is empty, the frame will /// complete when the next item is put in the channel. pub async fn get(self: *SelfChannel) T { - // TODO integrate this function with named return values - // so we can get rid of this extra result copy + // TODO https://github.com/ziglang/zig/issues/2765 var result: T = undefined; var my_tick_node = Loop.NextTickNode.init(@frame()); var queue_node = std.atomic.Queue(GetNode).Node.init(GetNode{ @@ -131,19 +128,19 @@ pub fn Channel(comptime T: type) type { // TODO test canceling a get() errdefer { - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Sub, 1, .SeqCst); const need_dispatch = !self.getters.remove(&queue_node); self.loop.cancelOnNextTick(&my_tick_node); if (need_dispatch) { // oops we made the get_count incorrect for a period of time. fix by dispatching. - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Add, 1, .SeqCst); self.dispatch(); } } suspend { self.getters.put(&queue_node); - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Add, 1, .SeqCst); self.dispatch(); } @@ -183,19 +180,19 @@ pub fn Channel(comptime T: type) type { // TODO test canceling getOrNull errdefer { _ = self.or_null_queue.remove(&or_null_node); - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Sub, 1, .SeqCst); const need_dispatch = !self.getters.remove(&queue_node); self.loop.cancelOnNextTick(&my_tick_node); if (need_dispatch) { // oops we made the get_count incorrect for a period of time. fix by dispatching. - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Add, 1, .SeqCst); self.dispatch(); } } suspend { self.getters.put(&queue_node); - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Add, 1, .SeqCst); self.or_null_queue.put(&or_null_node); self.dispatch(); @@ -205,21 +202,21 @@ pub fn Channel(comptime T: type) type { fn dispatch(self: *SelfChannel) void { // set the "need dispatch" flag - _ = @atomicRmw(u8, &self.need_dispatch, AtomicRmwOp.Xchg, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(u8, &self.need_dispatch, .Xchg, 1, .SeqCst); lock: while (true) { // set the lock flag - const prev_lock = @atomicRmw(u8, &self.dispatch_lock, AtomicRmwOp.Xchg, 1, AtomicOrder.SeqCst); + const prev_lock = @atomicRmw(u8, &self.dispatch_lock, .Xchg, 1, .SeqCst); if (prev_lock != 0) return; // clear the need_dispatch flag since we're about to do it - _ = @atomicRmw(u8, &self.need_dispatch, AtomicRmwOp.Xchg, 0, AtomicOrder.SeqCst); + _ = @atomicRmw(u8, &self.need_dispatch, .Xchg, 0, .SeqCst); while (true) { one_dispatch: { // later we correct these extra subtractions - var get_count = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); - var put_count = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + var get_count = @atomicRmw(usize, &self.get_count, .Sub, 1, .SeqCst); + var put_count = @atomicRmw(usize, &self.put_count, .Sub, 1, .SeqCst); // transfer self.buffer to self.getters while (self.buffer_len != 0) { @@ -238,7 +235,7 @@ pub fn Channel(comptime T: type) type { self.loop.onNextTick(get_node.tick_node); self.buffer_len -= 1; - get_count = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + get_count = @atomicRmw(usize, &self.get_count, .Sub, 1, .SeqCst); } // direct transfer self.putters to self.getters @@ -258,8 +255,8 @@ pub fn Channel(comptime T: type) type { self.loop.onNextTick(get_node.tick_node); self.loop.onNextTick(put_node.tick_node); - get_count = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); - put_count = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + get_count = @atomicRmw(usize, &self.get_count, .Sub, 1, .SeqCst); + put_count = @atomicRmw(usize, &self.put_count, .Sub, 1, .SeqCst); } // transfer self.putters to self.buffer @@ -271,13 +268,13 @@ pub fn Channel(comptime T: type) type { self.buffer_index +%= 1; self.buffer_len += 1; - put_count = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Sub, 1, AtomicOrder.SeqCst); + put_count = @atomicRmw(usize, &self.put_count, .Sub, 1, .SeqCst); } } // undo the extra subtractions - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); - _ = @atomicRmw(usize, &self.put_count, AtomicRmwOp.Add, 1, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Add, 1, .SeqCst); + _ = @atomicRmw(usize, &self.put_count, .Add, 1, .SeqCst); // All the "get or null" functions should resume now. var remove_count: usize = 0; @@ -286,18 +283,18 @@ pub fn Channel(comptime T: type) type { self.loop.onNextTick(or_null_node.data.data.tick_node); } if (remove_count != 0) { - _ = @atomicRmw(usize, &self.get_count, AtomicRmwOp.Sub, remove_count, AtomicOrder.SeqCst); + _ = @atomicRmw(usize, &self.get_count, .Sub, remove_count, .SeqCst); } // clear need-dispatch flag - const need_dispatch = @atomicRmw(u8, &self.need_dispatch, AtomicRmwOp.Xchg, 0, AtomicOrder.SeqCst); + const need_dispatch = @atomicRmw(u8, &self.need_dispatch, .Xchg, 0, .SeqCst); if (need_dispatch != 0) continue; - const my_lock = @atomicRmw(u8, &self.dispatch_lock, AtomicRmwOp.Xchg, 0, AtomicOrder.SeqCst); + const my_lock = @atomicRmw(u8, &self.dispatch_lock, .Xchg, 0, .SeqCst); assert(my_lock != 0); // we have to check again now that we unlocked - if (@atomicLoad(u8, &self.need_dispatch, AtomicOrder.SeqCst) != 0) continue :lock; + if (@atomicLoad(u8, &self.need_dispatch, .SeqCst) != 0) continue :lock; return; } @@ -327,16 +324,13 @@ test "std.event.Channel" { } async fn testChannelGetter(loop: *Loop, channel: *Channel(i32)) void { - const value1_promise = async channel.get(); - const value1 = await value1_promise; + const value1 = channel.get(); testing.expect(value1 == 1234); - const value2_promise = async channel.get(); - const value2 = await value2_promise; + const value2 = channel.get(); testing.expect(value2 == 4567); - const value3_promise = async channel.getOrNull(); - const value3 = await value3_promise; + const value3 = channel.getOrNull(); testing.expect(value3 == null); const last_put = async testPut(channel, 4444); -- cgit v1.2.3 From 2cb1f93894be3f48f0c49004515fa5e8190f69d9 Mon Sep 17 00:00:00 2001 From: yvt Date: Fri, 16 Aug 2019 23:54:28 +0900 Subject: correct LLVM subarch names for arm --- src/target.cpp | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- src/zig_llvm.cpp | 14 +++++++------- 2 files changed, 64 insertions(+), 8 deletions(-) (limited to 'src/target.cpp') diff --git a/src/target.cpp b/src/target.cpp index d1ae64acd4..8d73af6a01 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -651,7 +651,63 @@ ZigLLVM_SubArchType target_subarch_enum(SubArchList sub_arch_list, size_t i) { } const char *target_subarch_name(ZigLLVM_SubArchType subarch) { - return ZigLLVMGetSubArchTypeName(subarch); + switch (subarch) { + case ZigLLVM_NoSubArch: + return ""; + case ZigLLVM_ARMSubArch_v8_5a: + return "v8_5a"; + case ZigLLVM_ARMSubArch_v8_4a: + return "v8_4a"; + case ZigLLVM_ARMSubArch_v8_3a: + return "v8_3a"; + case ZigLLVM_ARMSubArch_v8_2a: + return "v8_2a"; + case ZigLLVM_ARMSubArch_v8_1a: + return "v8_1a"; + case ZigLLVM_ARMSubArch_v8: + return "v8"; + case ZigLLVM_ARMSubArch_v8r: + return "v8r"; + case ZigLLVM_ARMSubArch_v8m_baseline: + return "v8m_baseline"; + case ZigLLVM_ARMSubArch_v8m_mainline: + return "v8m_mainline"; + case ZigLLVM_ARMSubArch_v7: + return "v7"; + case ZigLLVM_ARMSubArch_v7em: + return "v7em"; + case ZigLLVM_ARMSubArch_v7m: + return "v7m"; + case ZigLLVM_ARMSubArch_v7s: + return "v7s"; + case ZigLLVM_ARMSubArch_v7k: + return "v7k"; + case ZigLLVM_ARMSubArch_v7ve: + return "v7ve"; + case ZigLLVM_ARMSubArch_v6: + return "v6"; + case ZigLLVM_ARMSubArch_v6m: + return "v6m"; + case ZigLLVM_ARMSubArch_v6k: + return "v6k"; + case ZigLLVM_ARMSubArch_v6t2: + return "v6t2"; + case ZigLLVM_ARMSubArch_v5: + return "v5"; + case ZigLLVM_ARMSubArch_v5te: + return "v5te"; + case ZigLLVM_ARMSubArch_v4t: + return "v4t"; + case ZigLLVM_KalimbaSubArch_v3: + return "v3"; + case ZigLLVM_KalimbaSubArch_v4: + return "v4"; + case ZigLLVM_KalimbaSubArch_v5: + return "v5"; + case ZigLLVM_MipsSubArch_r6: + return "r6"; + } + zig_unreachable(); } size_t target_subarch_list_count(void) { diff --git a/src/zig_llvm.cpp b/src/zig_llvm.cpp index 695f8b18ef..d9315ff549 100644 --- a/src/zig_llvm.cpp +++ b/src/zig_llvm.cpp @@ -785,23 +785,23 @@ const char *ZigLLVMGetSubArchTypeName(ZigLLVM_SubArchType sub_arch) { case ZigLLVM_NoSubArch: return ""; case ZigLLVM_ARMSubArch_v8_5a: - return "v8_5a"; + return "v8.5a"; case ZigLLVM_ARMSubArch_v8_4a: - return "v8_4a"; + return "v8.4a"; case ZigLLVM_ARMSubArch_v8_3a: - return "v8_3a"; + return "v8.3a"; case ZigLLVM_ARMSubArch_v8_2a: - return "v8_2a"; + return "v8.2a"; case ZigLLVM_ARMSubArch_v8_1a: - return "v8_1a"; + return "v8.1a"; case ZigLLVM_ARMSubArch_v8: return "v8"; case ZigLLVM_ARMSubArch_v8r: return "v8r"; case ZigLLVM_ARMSubArch_v8m_baseline: - return "v8m_baseline"; + return "v8m.base"; case ZigLLVM_ARMSubArch_v8m_mainline: - return "v8m_mainline"; + return "v8m.main"; case ZigLLVM_ARMSubArch_v7: return "v7"; case ZigLLVM_ARMSubArch_v7em: -- cgit v1.2.3