From 84f1893c18c4ef12dbe268ed6d11a11966a9d447 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Wed, 19 Feb 2020 21:30:36 -0500 Subject: remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261 --- src/stage2.cpp | 93 +++++++++++++++++++++++++++++++--------------------------- 1 file changed, 50 insertions(+), 43 deletions(-) (limited to 'src/stage2.cpp') diff --git a/src/stage2.cpp b/src/stage2.cpp index c3abe54d77..f3ae03242e 100644 --- a/src/stage2.cpp +++ b/src/stage2.cpp @@ -4,6 +4,7 @@ #include "stage2.h" #include "util.hpp" #include "zig_llvm.h" +#include "target.hpp" #include #include #include @@ -90,54 +91,60 @@ void stage2_progress_complete_one(Stage2ProgressNode *node) {} void stage2_progress_disable_tty(Stage2Progress *progress) {} void stage2_progress_update_node(Stage2ProgressNode *node, size_t completed_count, size_t estimated_total_items){} -struct Stage2CpuFeatures { - const char *llvm_cpu_name; - const char *llvm_cpu_features; - const char *builtin_str; - const char *cache_hash; -}; +Error stage2_target_parse(struct ZigTarget *target, const char *zig_triple, const char *mcpu) { + Error err; -Error stage2_cpu_features_parse(struct Stage2CpuFeatures **out, const char *zig_triple, - const char *cpu_name, const char *cpu_features) -{ if (zig_triple == nullptr) { - Stage2CpuFeatures *result = heap::c_allocator.create(); - result->llvm_cpu_name = ZigLLVMGetHostCPUName(); - result->llvm_cpu_features = ZigLLVMGetNativeFeatures(); - result->builtin_str = "arch.getBaselineCpuFeatures();\n"; - result->cache_hash = "native\n\n"; - *out = result; - return ErrorNone; - } - if (cpu_name == nullptr && cpu_features == nullptr) { - Stage2CpuFeatures *result = heap::c_allocator.create(); - result->builtin_str = "arch.getBaselineCpuFeatures();\n"; - result->cache_hash = "\n\n"; - *out = result; - return ErrorNone; + get_native_target(target); + + target->llvm_cpu_name = ZigLLVMGetHostCPUName(); + target->llvm_cpu_features = ZigLLVMGetNativeFeatures(); + target->builtin_str = "Target.Cpu.baseline(arch);\n"; + target->cache_hash = "native\n\n"; + } else { + // first initialize all to zero + *target = {}; + + SplitIterator it = memSplit(str(zig_triple), str("-")); + + Optional> opt_archsub = SplitIterator_next(&it); + Optional> opt_os = SplitIterator_next(&it); + Optional> opt_abi = SplitIterator_next(&it); + + if (!opt_archsub.is_some) + return ErrorMissingArchitecture; + + if ((err = target_parse_archsub(&target->arch, &target->sub_arch, + (char*)opt_archsub.value.ptr, opt_archsub.value.len))) + { + return err; + } + + if (!opt_os.is_some) + return ErrorMissingOperatingSystem; + + if ((err = target_parse_os(&target->os, (char*)opt_os.value.ptr, opt_os.value.len))) { + return err; + } + + if (opt_abi.is_some) { + if ((err = target_parse_abi(&target->abi, (char*)opt_abi.value.ptr, opt_abi.value.len))) { + return err; + } + } else { + target->abi = target_default_abi(target->arch, target->os); + } + + target->builtin_str = "Target.Cpu.baseline(arch);\n"; + target->cache_hash = "\n\n"; } - const char *msg = "stage0 called stage2_cpu_features_parse with non-null cpu name or features"; - stage2_panic(msg, strlen(msg)); -} + if (mcpu != nullptr) { + const char *msg = "stage0 can't handle CPU/features in the target"; + stage2_panic(msg, strlen(msg)); + } -void stage2_cpu_features_get_cache_hash(const Stage2CpuFeatures *cpu_features, - const char **ptr, size_t *len) -{ - *ptr = cpu_features->cache_hash; - *len = strlen(cpu_features->cache_hash); -} -const char *stage2_cpu_features_get_llvm_cpu(const Stage2CpuFeatures *cpu_features) { - return cpu_features->llvm_cpu_name; -} -const char *stage2_cpu_features_get_llvm_features(const Stage2CpuFeatures *cpu_features) { - return cpu_features->llvm_cpu_features; -} -void stage2_cpu_features_get_builtin_str(const Stage2CpuFeatures *cpu_features, - const char **ptr, size_t *len) -{ - *ptr = cpu_features->builtin_str; - *len = strlen(cpu_features->builtin_str); + return ErrorNone; } int stage2_cmd_targets(const char *zig_triple) { -- cgit v1.2.3 From 0f016b368de2ac93a298ab771646931329062fb5 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Thu, 20 Feb 2020 18:31:17 -0500 Subject: support -mcpu=baseline, both in stage1 and stage2 See e381a42de9c0f0c5439a926b0ac99026a0373f49 for more details. This is set up so that if we wish to make "baseline" depend on the OS in the future, it is possible to do that. --- lib/std/target.zig | 32 ++++++++++++++++++-------------- src-self-hosted/stage2.zig | 4 ++-- src/stage2.cpp | 27 ++++++++++++++++++--------- test/compile_errors.zig | 3 +-- test/tests.zig | 8 ++++---- test/translate_c.zig | 3 +-- 6 files changed, 44 insertions(+), 33 deletions(-) (limited to 'src/stage2.cpp') diff --git a/lib/std/target.zig b/lib/std/target.zig index 3d04e3424e..875ccda57f 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -726,8 +726,7 @@ pub const Target = union(enum) { /// Looks like "name+a+b-c-d+e", where "name" is a CPU Model name, "a", "b", and "e" /// are examples of CPU features to add to the set, and "c" and "d" are examples of CPU features /// to remove from the set. - /// The default value of `null` means to use the "baseline" feature set. - cpu: ?[]const u8 = null, + cpu_features: []const u8 = "baseline", }; pub fn parse(args: ParseOptions) !Target { @@ -742,23 +741,29 @@ pub const Target = union(enum) { const abi = if (abi_name) |n| try Abi.parse(n) else Abi.default(arch, os); const all_features = arch.allFeaturesList(); - const cpu: Cpu = if (args.cpu) |cpu_text| blk: { - var index: usize = 0; - while (index < cpu_text.len and cpu_text[index] != '+' and cpu_text[index] != '-') { - index += 1; - } - const cpu_name = cpu_text[0..index]; + var index: usize = 0; + while (index < args.cpu_features.len and + args.cpu_features[index] != '+' and + args.cpu_features[index] != '-') + { + index += 1; + } + const cpu_name = args.cpu_features[0..index]; + const cpu: Cpu = if (mem.eql(u8, cpu_name, "baseline")) Cpu.baseline(arch) else blk: { const cpu_model = try arch.parseCpuModel(cpu_name); var set = cpu_model.features; - while (index < cpu_text.len) { - const op = cpu_text[index]; + while (index < args.cpu_features.len) { + const op = args.cpu_features[index]; index += 1; const start = index; - while (index < cpu_text.len and cpu_text[index] != '+' and cpu_text[index] != '-') { + while (index < args.cpu_features.len and + args.cpu_features[index] != '+' and + args.cpu_features[index] != '-') + { index += 1; } - const feature_name = cpu_text[start..index]; + const feature_name = args.cpu_features[start..index]; for (all_features) |feature, feat_index_usize| { const feat_index = @intCast(Cpu.Feature.Set.Index, feat_index_usize); if (mem.eql(u8, feature_name, feature.name)) { @@ -779,8 +784,7 @@ pub const Target = union(enum) { .model = cpu_model, .features = set, }; - } else Cpu.baseline(arch); - + }; var cross = Cross{ .cpu = cpu, .os = os, diff --git a/src-self-hosted/stage2.zig b/src-self-hosted/stage2.zig index 048686190d..f7c4306cd5 100644 --- a/src-self-hosted/stage2.zig +++ b/src-self-hosted/stage2.zig @@ -675,8 +675,8 @@ fn stage2TargetParse( ) !void { const target: Target = if (zig_triple_oz) |zig_triple_z| blk: { const zig_triple = mem.toSliceConst(u8, zig_triple_z); - const mcpu = if (mcpu_oz) |mcpu_z| mem.toSliceConst(u8, mcpu_z) else null; - break :blk try Target.parse(.{ .arch_os_abi = zig_triple, .cpu = mcpu }); + const mcpu = if (mcpu_oz) |mcpu_z| mem.toSliceConst(u8, mcpu_z) else "baseline"; + break :blk try Target.parse(.{ .arch_os_abi = zig_triple, .cpu_features = mcpu }); } else Target.Native; try stage1_target.fromTarget(target); diff --git a/src/stage2.cpp b/src/stage2.cpp index f3ae03242e..035ce5a008 100644 --- a/src/stage2.cpp +++ b/src/stage2.cpp @@ -97,10 +97,20 @@ Error stage2_target_parse(struct ZigTarget *target, const char *zig_triple, cons if (zig_triple == nullptr) { get_native_target(target); - target->llvm_cpu_name = ZigLLVMGetHostCPUName(); - target->llvm_cpu_features = ZigLLVMGetNativeFeatures(); - target->builtin_str = "Target.Cpu.baseline(arch);\n"; - target->cache_hash = "native\n\n"; + if (mcpu == nullptr) { + target->llvm_cpu_name = ZigLLVMGetHostCPUName(); + target->llvm_cpu_features = ZigLLVMGetNativeFeatures(); + target->builtin_str = "Target.Cpu.baseline(arch);\n"; + target->cache_hash = "native\n\n"; + } else if (strcmp(mcpu, "baseline") == 0) { + target->llvm_cpu_name = ""; + target->llvm_cpu_features = ""; + target->builtin_str = "Target.Cpu.baseline(arch);\n"; + target->cache_hash = "baseline\n\n"; + } else { + const char *msg = "stage0 can't handle CPU/features in the target"; + stage2_panic(msg, strlen(msg)); + } } else { // first initialize all to zero *target = {}; @@ -135,15 +145,14 @@ Error stage2_target_parse(struct ZigTarget *target, const char *zig_triple, cons target->abi = target_default_abi(target->arch, target->os); } + if (mcpu != nullptr && strcmp(mcpu, "baseline") != 0) { + const char *msg = "stage0 can't handle CPU/features in the target"; + stage2_panic(msg, strlen(msg)); + } target->builtin_str = "Target.Cpu.baseline(arch);\n"; target->cache_hash = "\n\n"; } - if (mcpu != nullptr) { - const char *msg = "stage0 can't handle CPU/features in the target"; - stage2_panic(msg, strlen(msg)); - } - return ErrorNone; } diff --git a/test/compile_errors.zig b/test/compile_errors.zig index 9f2b3716b0..4d133a1b5c 100644 --- a/test/compile_errors.zig +++ b/test/compile_errors.zig @@ -350,8 +350,7 @@ pub fn addCases(cases: *tests.CompileErrorContext) void { }); tc.target = Target{ .Cross = .{ - .arch = .wasm32, - .cpu_features = Target.Arch.wasm32.getBaselineCpuFeatures(), + .cpu = Target.Cpu.baseline(.wasm32), .os = .wasi, .abi = .none, }, diff --git a/test/tests.zig b/test/tests.zig index 3190126208..f12f7f83d4 100644 --- a/test/tests.zig +++ b/test/tests.zig @@ -135,13 +135,13 @@ const test_targets = blk: { TestTarget{ .target = Target.parse(.{ .arch_os_abi = "arm-linux-none", - .cpu = "generic+v8a", + .cpu_features = "generic+v8a", }) catch unreachable, }, TestTarget{ .target = Target.parse(.{ .arch_os_abi = "arm-linux-musleabihf", - .cpu = "generic+v8a", + .cpu_features = "generic+v8a", }) catch unreachable, .link_libc = true, }, @@ -149,7 +149,7 @@ const test_targets = blk: { //TestTarget{ // .target = Target.parse(.{ // .arch_os_abi = "arm-linux-gnueabihf", - // .cpu = "generic+v8a", + // .cpu_features = "generic+v8a", // }) catch unreachable, // .link_libc = true, //}, @@ -449,7 +449,7 @@ pub fn addPkgTests( const ArchTag = @TagType(builtin.Arch); if (test_target.disable_native and test_target.target.getOs() == builtin.os and - @as(ArchTag, test_target.target.getArch()) == @as(ArchTag, builtin.arch)) + test_target.target.getArch() == builtin.arch) { continue; } diff --git a/test/translate_c.zig b/test/translate_c.zig index b69142e864..2351a6c94f 100644 --- a/test/translate_c.zig +++ b/test/translate_c.zig @@ -1095,10 +1095,9 @@ pub fn addCases(cases: *tests.TranslateCContext) void { cases.addWithTarget("Calling convention", tests.Target{ .Cross = .{ + .cpu = Target.Cpu.baseline(.i386), .os = .linux, - .arch = .i386, .abi = .none, - .cpu_features = Target.Arch.i386.getBaselineCpuFeatures(), }, }, \\void __attribute__((fastcall)) foo1(float *a); -- cgit v1.2.3 From 61c67a9833c312678289272e5e0547a78cbd299c Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Fri, 21 Feb 2020 11:47:34 -0500 Subject: remove sub-arch from stage1 --- src-self-hosted/stage2.zig | 7 +- src/codegen.cpp | 3 - src/glibc.cpp | 6 +- src/stage2.cpp | 4 +- src/stage2.h | 5 +- src/target.cpp | 279 ++------------------------------------------- src/target.hpp | 21 +--- src/zig_llvm.cpp | 94 +-------------- src/zig_llvm.h | 38 +----- 9 files changed, 17 insertions(+), 440 deletions(-) (limited to 'src/stage2.cpp') diff --git a/src-self-hosted/stage2.zig b/src-self-hosted/stage2.zig index 6a537a486a..d99f436a75 100644 --- a/src-self-hosted/stage2.zig +++ b/src-self-hosted/stage2.zig @@ -909,12 +909,11 @@ export fn stage2_libc_render(stage1_libc: *Stage2LibCInstallation, output_file: // ABI warning const Stage2Target = extern struct { arch: c_int, - sub_arch: c_int, - vendor: c_int, - abi: c_int, + abi: c_int, os: c_int, + is_native: bool, glibc_version: ?*Stage2GLibCVersion, // null means default @@ -928,7 +927,6 @@ const Stage2Target = extern struct { if (in_target.is_native) return .Native; const in_arch = in_target.arch - 1; // skip over ZigLLVM_UnknownArch - const in_sub_arch = in_target.sub_arch - 1; // skip over ZigLLVM_NoSubArch const in_os = in_target.os; const in_abi = in_target.abi; @@ -954,7 +952,6 @@ const Stage2Target = extern struct { }; self.* = .{ .arch = @enumToInt(target.getArch()) + 1, // skip over ZigLLVM_UnknownArch - .sub_arch = 0, .vendor = 0, .os = @enumToInt(target.getOs()), .abi = @enumToInt(target.getAbi()), diff --git a/src/codegen.cpp b/src/codegen.cpp index b5d621dd7c..6e48f9be42 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -8711,7 +8711,6 @@ static Error define_builtin_compile_vars(CodeGen *g) { cache_int(&cache_hash, g->code_model); cache_int(&cache_hash, g->zig_target->is_native); cache_int(&cache_hash, g->zig_target->arch); - cache_int(&cache_hash, g->zig_target->sub_arch); cache_int(&cache_hash, g->zig_target->vendor); cache_int(&cache_hash, g->zig_target->os); cache_int(&cache_hash, g->zig_target->abi); @@ -9616,7 +9615,6 @@ Error create_c_object_cache(CodeGen *g, CacheHash **out_cache_hash, bool verbose cache_list_of_str(cache_hash, g->libc_include_dir_list, g->libc_include_dir_len); cache_int(cache_hash, g->zig_target->is_native); cache_int(cache_hash, g->zig_target->arch); - cache_int(cache_hash, g->zig_target->sub_arch); cache_int(cache_hash, g->zig_target->vendor); cache_int(cache_hash, g->zig_target->os); cache_int(cache_hash, g->zig_target->abi); @@ -10380,7 +10378,6 @@ static Error check_cache(CodeGen *g, Buf *manifest_dir, Buf *digest) { cache_int(ch, g->out_type); cache_bool(ch, g->zig_target->is_native); cache_int(ch, g->zig_target->arch); - cache_int(ch, g->zig_target->sub_arch); cache_int(ch, g->zig_target->vendor); cache_int(ch, g->zig_target->os); cache_int(ch, g->zig_target->abi); diff --git a/src/glibc.cpp b/src/glibc.cpp index ec45b6afa7..849aac6c77 100644 --- a/src/glibc.cpp +++ b/src/glibc.cpp @@ -116,10 +116,8 @@ Error glibc_load_metadata(ZigGLibCAbi **out_result, Buf *zig_lib_dir, bool verbo assert(opt_abi.is_some); - err = target_parse_archsub(&target->arch, &target->sub_arch, - (char*)opt_arch.value.ptr, opt_arch.value.len); - // there's no sub arch so we might get an error, but the arch is still populated - assert(err == ErrorNone || err == ErrorUnknownArchitecture); + err = target_parse_arch(&target->arch, (char*)opt_arch.value.ptr, opt_arch.value.len); + assert(err == ErrorNone); target->os = OsLinux; diff --git a/src/stage2.cpp b/src/stage2.cpp index f5bfc1001c..736f11622e 100644 --- a/src/stage2.cpp +++ b/src/stage2.cpp @@ -125,9 +125,7 @@ Error stage2_target_parse(struct ZigTarget *target, const char *zig_triple, cons if (!opt_archsub.is_some) return ErrorMissingArchitecture; - if ((err = target_parse_archsub(&target->arch, &target->sub_arch, - (char*)opt_archsub.value.ptr, opt_archsub.value.len))) - { + if ((err = target_parse_arch(&target->arch, (char*)opt_archsub.value.ptr, opt_archsub.value.len))) { return err; } diff --git a/src/stage2.h b/src/stage2.h index fe49c943a0..e6db241e88 100644 --- a/src/stage2.h +++ b/src/stage2.h @@ -279,12 +279,11 @@ struct Stage2TargetData; // ABI warning struct ZigTarget { enum ZigLLVM_ArchType arch; - enum ZigLLVM_SubArchType sub_arch; - enum ZigLLVM_VendorType vendor; - enum ZigLLVM_EnvironmentType abi; + enum ZigLLVM_EnvironmentType abi; Os os; + bool is_native; struct ZigGLibCVersion *glibc_version; // null means default diff --git a/src/target.cpp b/src/target.cpp index fb064c4849..0a3fb3da5f 100644 --- a/src/target.cpp +++ b/src/target.cpp @@ -15,60 +15,6 @@ #include -static const SubArchList subarch_list_list[] = { - SubArchListNone, - SubArchListArm32, - SubArchListArm64, - SubArchListKalimba, - SubArchListMips, -}; - -static const ZigLLVM_SubArchType subarch_list_arm32[] = { - ZigLLVM_ARMSubArch_v8_5a, - ZigLLVM_ARMSubArch_v8_4a, - ZigLLVM_ARMSubArch_v8_3a, - ZigLLVM_ARMSubArch_v8_2a, - ZigLLVM_ARMSubArch_v8_1a, - ZigLLVM_ARMSubArch_v8, - ZigLLVM_ARMSubArch_v8r, - ZigLLVM_ARMSubArch_v8m_baseline, - ZigLLVM_ARMSubArch_v8m_mainline, - ZigLLVM_ARMSubArch_v8_1m_mainline, - ZigLLVM_ARMSubArch_v7, - ZigLLVM_ARMSubArch_v7em, - ZigLLVM_ARMSubArch_v7m, - ZigLLVM_ARMSubArch_v7s, - ZigLLVM_ARMSubArch_v7k, - ZigLLVM_ARMSubArch_v7ve, - ZigLLVM_ARMSubArch_v6, - ZigLLVM_ARMSubArch_v6m, - ZigLLVM_ARMSubArch_v6k, - ZigLLVM_ARMSubArch_v6t2, - ZigLLVM_ARMSubArch_v5, - ZigLLVM_ARMSubArch_v5te, - ZigLLVM_ARMSubArch_v4t, - -}; - -static const ZigLLVM_SubArchType subarch_list_arm64[] = { - ZigLLVM_ARMSubArch_v8_5a, - ZigLLVM_ARMSubArch_v8_4a, - ZigLLVM_ARMSubArch_v8_3a, - ZigLLVM_ARMSubArch_v8_2a, - ZigLLVM_ARMSubArch_v8_1a, - ZigLLVM_ARMSubArch_v8, -}; - -static const ZigLLVM_SubArchType subarch_list_kalimba[] = { - ZigLLVM_KalimbaSubArch_v5, - ZigLLVM_KalimbaSubArch_v4, - ZigLLVM_KalimbaSubArch_v3, -}; - -static const ZigLLVM_SubArchType subarch_list_mips[] = { - ZigLLVM_MipsSubArch_r6, -}; - static const ZigLLVM_ArchType arch_list[] = { ZigLLVM_arm, // ARM (little endian): arm, armv.*, xscale ZigLLVM_armeb, // ARM (big endian): armeb @@ -509,7 +455,6 @@ void get_native_target(ZigTarget *target) { ZigLLVM_ObjectFormatType oformat; // ignored; based on arch/os ZigLLVMGetNativeTarget( &target->arch, - &target->sub_arch, &target->vendor, &os_type, &target->abi, @@ -535,223 +480,18 @@ void target_init_default_glibc_version(ZigTarget *target) { *target->glibc_version = {2, 17, 0}; } -Error target_parse_archsub(ZigLLVM_ArchType *out_arch, ZigLLVM_SubArchType *out_sub, - const char *archsub_ptr, size_t archsub_len) -{ +Error target_parse_arch(ZigLLVM_ArchType *out_arch, const char *arch_ptr, size_t arch_len) { *out_arch = ZigLLVM_UnknownArch; - *out_sub = ZigLLVM_NoSubArch; for (size_t arch_i = 0; arch_i < array_length(arch_list); arch_i += 1) { ZigLLVM_ArchType arch = arch_list[arch_i]; - SubArchList sub_arch_list = target_subarch_list(arch); - size_t subarch_count = target_subarch_count(sub_arch_list); - if (mem_eql_str(archsub_ptr, archsub_len, target_arch_name(arch))) { + if (mem_eql_str(arch_ptr, arch_len, target_arch_name(arch))) { *out_arch = arch; - if (subarch_count == 0) { - return ErrorNone; - } - } - for (size_t sub_i = 0; sub_i < subarch_count; sub_i += 1) { - ZigLLVM_SubArchType sub = target_subarch_enum(sub_arch_list, sub_i); - char arch_name[64]; - int n = sprintf(arch_name, "%s%s", target_arch_name(arch), target_subarch_name(sub)); - if (mem_eql_mem(arch_name, n, archsub_ptr, archsub_len)) { - *out_arch = arch; - *out_sub = sub; - return ErrorNone; - } + return ErrorNone; } } return ErrorUnknownArchitecture; } -SubArchList target_subarch_list(ZigLLVM_ArchType arch) { - switch (arch) { - case ZigLLVM_UnknownArch: - zig_unreachable(); - case ZigLLVM_arm: - case ZigLLVM_armeb: - case ZigLLVM_thumb: - case ZigLLVM_thumbeb: - return SubArchListArm32; - - case ZigLLVM_aarch64: - case ZigLLVM_aarch64_be: - case ZigLLVM_aarch64_32: - return SubArchListArm64; - - case ZigLLVM_kalimba: - return SubArchListKalimba; - - case ZigLLVM_arc: - case ZigLLVM_avr: - case ZigLLVM_bpfel: - case ZigLLVM_bpfeb: - case ZigLLVM_hexagon: - case ZigLLVM_mips: - case ZigLLVM_mipsel: - case ZigLLVM_mips64: - case ZigLLVM_mips64el: - case ZigLLVM_msp430: - case ZigLLVM_ppc: - case ZigLLVM_ppc64: - case ZigLLVM_ppc64le: - case ZigLLVM_r600: - case ZigLLVM_amdgcn: - case ZigLLVM_riscv32: - case ZigLLVM_riscv64: - case ZigLLVM_sparc: - case ZigLLVM_sparcv9: - case ZigLLVM_sparcel: - case ZigLLVM_systemz: - case ZigLLVM_tce: - case ZigLLVM_tcele: - case ZigLLVM_x86: - case ZigLLVM_x86_64: - case ZigLLVM_xcore: - case ZigLLVM_nvptx: - case ZigLLVM_nvptx64: - case ZigLLVM_le32: - case ZigLLVM_le64: - case ZigLLVM_amdil: - case ZigLLVM_amdil64: - case ZigLLVM_hsail: - case ZigLLVM_hsail64: - case ZigLLVM_spir: - case ZigLLVM_spir64: - case ZigLLVM_shave: - case ZigLLVM_lanai: - case ZigLLVM_wasm32: - case ZigLLVM_wasm64: - case ZigLLVM_renderscript32: - case ZigLLVM_renderscript64: - return SubArchListNone; - } - zig_unreachable(); -} - -size_t target_subarch_count(SubArchList sub_arch_list) { - switch (sub_arch_list) { - case SubArchListNone: - return 0; - case SubArchListArm32: - return array_length(subarch_list_arm32); - case SubArchListArm64: - return array_length(subarch_list_arm64); - case SubArchListKalimba: - return array_length(subarch_list_kalimba); - case SubArchListMips: - return array_length(subarch_list_mips); - } - zig_unreachable(); -} - -ZigLLVM_SubArchType target_subarch_enum(SubArchList sub_arch_list, size_t i) { - switch (sub_arch_list) { - case SubArchListNone: - zig_unreachable(); - case SubArchListArm32: - assert(i < array_length(subarch_list_arm32)); - return subarch_list_arm32[i]; - case SubArchListArm64: - assert(i < array_length(subarch_list_arm64)); - return subarch_list_arm64[i]; - case SubArchListKalimba: - assert(i < array_length(subarch_list_kalimba)); - return subarch_list_kalimba[i]; - case SubArchListMips: - assert(i < array_length(subarch_list_mips)); - return subarch_list_mips[i]; - } - zig_unreachable(); -} - -const char *target_subarch_name(ZigLLVM_SubArchType subarch) { - switch (subarch) { - case ZigLLVM_NoSubArch: - return ""; - case ZigLLVM_ARMSubArch_v8_5a: - return "v8_5a"; - case ZigLLVM_ARMSubArch_v8_4a: - return "v8_4a"; - case ZigLLVM_ARMSubArch_v8_3a: - return "v8_3a"; - case ZigLLVM_ARMSubArch_v8_2a: - return "v8_2a"; - case ZigLLVM_ARMSubArch_v8_1a: - return "v8_1a"; - case ZigLLVM_ARMSubArch_v8: - return "v8a"; - case ZigLLVM_ARMSubArch_v8r: - return "v8r"; - case ZigLLVM_ARMSubArch_v8m_baseline: - return "v8m_baseline"; - case ZigLLVM_ARMSubArch_v8m_mainline: - return "v8m_mainline"; - case ZigLLVM_ARMSubArch_v8_1m_mainline: - return "v8_1m_mainline"; - case ZigLLVM_ARMSubArch_v7: - return "v7a"; - case ZigLLVM_ARMSubArch_v7em: - return "v7em"; - case ZigLLVM_ARMSubArch_v7m: - return "v7m"; - case ZigLLVM_ARMSubArch_v7s: - return "v7s"; - case ZigLLVM_ARMSubArch_v7k: - return "v7k"; - case ZigLLVM_ARMSubArch_v7ve: - return "v7ve"; - case ZigLLVM_ARMSubArch_v6: - return "v6"; - case ZigLLVM_ARMSubArch_v6m: - return "v6m"; - case ZigLLVM_ARMSubArch_v6k: - return "v6k"; - case ZigLLVM_ARMSubArch_v6t2: - return "v6t2"; - case ZigLLVM_ARMSubArch_v5: - return "v5"; - case ZigLLVM_ARMSubArch_v5te: - return "v5te"; - case ZigLLVM_ARMSubArch_v4t: - return "v4t"; - case ZigLLVM_KalimbaSubArch_v3: - return "v3"; - case ZigLLVM_KalimbaSubArch_v4: - return "v4"; - case ZigLLVM_KalimbaSubArch_v5: - return "v5"; - case ZigLLVM_MipsSubArch_r6: - return "r6"; - } - zig_unreachable(); -} - -size_t target_subarch_list_count(void) { - return array_length(subarch_list_list); -} - -SubArchList target_subarch_list_enum(size_t index) { - assert(index < array_length(subarch_list_list)); - return subarch_list_list[index]; -} - -const char *target_subarch_list_name(SubArchList sub_arch_list) { - switch (sub_arch_list) { - case SubArchListNone: - return "None"; - case SubArchListArm32: - return "Arm32"; - case SubArchListArm64: - return "Arm64"; - case SubArchListKalimba: - return "Kalimba"; - case SubArchListMips: - return "Mips"; - } - zig_unreachable(); -} - Error target_parse_os(Os *out_os, const char *os_ptr, size_t os_len) { for (size_t i = 0; i < array_length(os_list); i += 1) { Os os = os_list[i]; @@ -794,18 +534,16 @@ void init_all_targets(void) { void target_triple_zig(Buf *triple, const ZigTarget *target) { buf_resize(triple, 0); - buf_appendf(triple, "%s%s-%s-%s", + buf_appendf(triple, "%s-%s-%s", target_arch_name(target->arch), - target_subarch_name(target->sub_arch), target_os_name(target->os), target_abi_name(target->abi)); } void target_triple_llvm(Buf *triple, const ZigTarget *target) { buf_resize(triple, 0); - buf_appendf(triple, "%s%s-%s-%s-%s", + buf_appendf(triple, "%s-%s-%s-%s", ZigLLVMGetArchTypeName(target->arch), - ZigLLVMGetSubArchTypeName(target->sub_arch), ZigLLVMGetVendorTypeName(target->vendor), ZigLLVMGetOSTypeName(get_llvm_os_type(target->os)), ZigLLVMGetEnvironmentTypeName(target->abi)); @@ -1182,10 +920,8 @@ bool target_can_exec(const ZigTarget *host_target, const ZigTarget *guest_target return true; } - if (guest_target->os == host_target->os && guest_target->arch == host_target->arch && - guest_target->sub_arch == host_target->sub_arch) - { - // OS, arch, and sub-arch match + if (guest_target->os == host_target->os && guest_target->arch == host_target->arch) { + // OS and arch match return true; } @@ -1607,7 +1343,6 @@ void target_libc_enum(size_t index, ZigTarget *out_target) { out_target->arch = libcs_available[index].arch; out_target->os = libcs_available[index].os; out_target->abi = libcs_available[index].abi; - out_target->sub_arch = ZigLLVM_NoSubArch; out_target->vendor = ZigLLVM_UnknownVendor; out_target->is_native = false; } diff --git a/src/target.hpp b/src/target.hpp index 95acbe259e..9396eb2623 100644 --- a/src/target.hpp +++ b/src/target.hpp @@ -12,15 +12,6 @@ struct Buf; -// Synchronize with target.cpp::subarch_list_list -enum SubArchList { - SubArchListNone, - SubArchListArm32, - SubArchListArm64, - SubArchListKalimba, - SubArchListMips, -}; - enum TargetSubsystem { TargetSubsystemConsole, TargetSubsystemWindows, @@ -51,8 +42,7 @@ enum CIntType { }; Error target_parse_triple(ZigTarget *target, const char *triple, const char *mcpu); -Error target_parse_archsub(ZigLLVM_ArchType *arch, ZigLLVM_SubArchType *sub, - const char *archsub_ptr, size_t archsub_len); +Error target_parse_arch(ZigLLVM_ArchType *arch, const char *arch_ptr, size_t arch_len); Error target_parse_os(Os *os, const char *os_ptr, size_t os_len); Error target_parse_abi(ZigLLVM_EnvironmentType *abi, const char *abi_ptr, size_t abi_len); @@ -63,15 +53,6 @@ size_t target_arch_count(void); ZigLLVM_ArchType target_arch_enum(size_t index); const char *target_arch_name(ZigLLVM_ArchType arch); -SubArchList target_subarch_list(ZigLLVM_ArchType arch); -size_t target_subarch_count(SubArchList sub_arch_list); -ZigLLVM_SubArchType target_subarch_enum(SubArchList subarch_list, size_t index); -const char *target_subarch_name(ZigLLVM_SubArchType subarch); - -size_t target_subarch_list_count(void); -SubArchList target_subarch_list_enum(size_t index); -const char *target_subarch_list_name(SubArchList sub_arch_list); - const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch); size_t target_vendor_count(void); diff --git a/src/zig_llvm.cpp b/src/zig_llvm.cpp index 64706500d5..aed2944f62 100644 --- a/src/zig_llvm.cpp +++ b/src/zig_llvm.cpp @@ -806,7 +806,7 @@ const char *ZigLLVMGetEnvironmentTypeName(ZigLLVM_EnvironmentType env_type) { return (const char*)Triple::getEnvironmentTypeName((Triple::EnvironmentType)env_type).bytes_begin(); } -void ZigLLVMGetNativeTarget(ZigLLVM_ArchType *arch_type, ZigLLVM_SubArchType *sub_arch_type, +void ZigLLVMGetNativeTarget(ZigLLVM_ArchType *arch_type, ZigLLVM_VendorType *vendor_type, ZigLLVM_OSType *os_type, ZigLLVM_EnvironmentType *environ_type, ZigLLVM_ObjectFormatType *oformat) { @@ -814,7 +814,6 @@ void ZigLLVMGetNativeTarget(ZigLLVM_ArchType *arch_type, ZigLLVM_SubArchType *su Triple triple(Triple::normalize(native_triple)); *arch_type = (ZigLLVM_ArchType)triple.getArch(); - *sub_arch_type = (ZigLLVM_SubArchType)triple.getSubArch(); *vendor_type = (ZigLLVM_VendorType)triple.getVendor(); *os_type = (ZigLLVM_OSType)triple.getOS(); *environ_type = (ZigLLVM_EnvironmentType)triple.getEnvironment(); @@ -823,68 +822,6 @@ void ZigLLVMGetNativeTarget(ZigLLVM_ArchType *arch_type, ZigLLVM_SubArchType *su free(native_triple); } -const char *ZigLLVMGetSubArchTypeName(ZigLLVM_SubArchType sub_arch) { - switch (sub_arch) { - case ZigLLVM_NoSubArch: - return ""; - case ZigLLVM_ARMSubArch_v8_5a: - return "v8.5a"; - case ZigLLVM_ARMSubArch_v8_4a: - return "v8.4a"; - case ZigLLVM_ARMSubArch_v8_3a: - return "v8.3a"; - case ZigLLVM_ARMSubArch_v8_2a: - return "v8.2a"; - case ZigLLVM_ARMSubArch_v8_1a: - return "v8.1a"; - case ZigLLVM_ARMSubArch_v8: - return "v8a"; - case ZigLLVM_ARMSubArch_v8r: - return "v8r"; - case ZigLLVM_ARMSubArch_v8m_baseline: - return "v8m.base"; - case ZigLLVM_ARMSubArch_v8m_mainline: - return "v8m.main"; - case ZigLLVM_ARMSubArch_v8_1m_mainline: - return "v8.1m.main"; - case ZigLLVM_ARMSubArch_v7: - return "v7a"; - case ZigLLVM_ARMSubArch_v7em: - return "v7em"; - case ZigLLVM_ARMSubArch_v7m: - return "v7m"; - case ZigLLVM_ARMSubArch_v7s: - return "v7s"; - case ZigLLVM_ARMSubArch_v7k: - return "v7k"; - case ZigLLVM_ARMSubArch_v7ve: - return "v7ve"; - case ZigLLVM_ARMSubArch_v6: - return "v6"; - case ZigLLVM_ARMSubArch_v6m: - return "v6m"; - case ZigLLVM_ARMSubArch_v6k: - return "v6k"; - case ZigLLVM_ARMSubArch_v6t2: - return "v6t2"; - case ZigLLVM_ARMSubArch_v5: - return "v5"; - case ZigLLVM_ARMSubArch_v5te: - return "v5te"; - case ZigLLVM_ARMSubArch_v4t: - return "v4t"; - case ZigLLVM_KalimbaSubArch_v3: - return "v3"; - case ZigLLVM_KalimbaSubArch_v4: - return "v4"; - case ZigLLVM_KalimbaSubArch_v5: - return "v5"; - case ZigLLVM_MipsSubArch_r6: - return "r6"; - } - abort(); -} - void ZigLLVMAddModuleDebugInfoFlag(LLVMModuleRef module) { unwrap(module)->addModuleFlag(Module::Warning, "Debug Info Version", DEBUG_METADATA_VERSION); unwrap(module)->addModuleFlag(Module::Warning, "Dwarf Version", 4); @@ -1218,35 +1155,6 @@ static_assert((Triple::ArchType)ZigLLVM_renderscript32 == Triple::renderscript32 static_assert((Triple::ArchType)ZigLLVM_renderscript64 == Triple::renderscript64, ""); static_assert((Triple::ArchType)ZigLLVM_LastArchType == Triple::LastArchType, ""); -static_assert((Triple::SubArchType)ZigLLVM_NoSubArch == Triple::NoSubArch, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8_4a == Triple::ARMSubArch_v8_4a, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8_3a == Triple::ARMSubArch_v8_3a, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8_2a == Triple::ARMSubArch_v8_2a, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8_1a == Triple::ARMSubArch_v8_1a, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8 == Triple::ARMSubArch_v8, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8r == Triple::ARMSubArch_v8r, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8m_baseline == Triple::ARMSubArch_v8m_baseline, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8m_mainline == Triple::ARMSubArch_v8m_mainline, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v8_1m_mainline == Triple::ARMSubArch_v8_1m_mainline, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v7 == Triple::ARMSubArch_v7, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v7em == Triple::ARMSubArch_v7em, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v7m == Triple::ARMSubArch_v7m, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v7s == Triple::ARMSubArch_v7s, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v7k == Triple::ARMSubArch_v7k, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v7ve == Triple::ARMSubArch_v7ve, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v6 == Triple::ARMSubArch_v6, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v6m == Triple::ARMSubArch_v6m, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v6k == Triple::ARMSubArch_v6k, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v6t2 == Triple::ARMSubArch_v6t2, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v5 == Triple::ARMSubArch_v5, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v5te == Triple::ARMSubArch_v5te, ""); -static_assert((Triple::SubArchType)ZigLLVM_ARMSubArch_v4t == Triple::ARMSubArch_v4t, ""); -static_assert((Triple::SubArchType)ZigLLVM_KalimbaSubArch_v3 == Triple::KalimbaSubArch_v3, ""); -static_assert((Triple::SubArchType)ZigLLVM_KalimbaSubArch_v4 == Triple::KalimbaSubArch_v4, ""); -static_assert((Triple::SubArchType)ZigLLVM_KalimbaSubArch_v5 == Triple::KalimbaSubArch_v5, ""); -static_assert((Triple::SubArchType)ZigLLVM_KalimbaSubArch_v5 == Triple::KalimbaSubArch_v5, ""); -static_assert((Triple::SubArchType)ZigLLVM_MipsSubArch_r6 == Triple::MipsSubArch_r6, ""); - static_assert((Triple::VendorType)ZigLLVM_UnknownVendor == Triple::UnknownVendor, ""); static_assert((Triple::VendorType)ZigLLVM_Apple == Triple::Apple, ""); static_assert((Triple::VendorType)ZigLLVM_PC == Triple::PC, ""); diff --git a/src/zig_llvm.h b/src/zig_llvm.h index 95751cd08a..95f5926ec7 100644 --- a/src/zig_llvm.h +++ b/src/zig_llvm.h @@ -324,41 +324,6 @@ enum ZigLLVM_ArchType { ZigLLVM_LastArchType = ZigLLVM_renderscript64 }; -// synchronize with lists in target.cpp -enum ZigLLVM_SubArchType { - ZigLLVM_NoSubArch, - - ZigLLVM_ARMSubArch_v8_5a, - ZigLLVM_ARMSubArch_v8_4a, - ZigLLVM_ARMSubArch_v8_3a, - ZigLLVM_ARMSubArch_v8_2a, - ZigLLVM_ARMSubArch_v8_1a, - ZigLLVM_ARMSubArch_v8, - ZigLLVM_ARMSubArch_v8r, - ZigLLVM_ARMSubArch_v8m_baseline, - ZigLLVM_ARMSubArch_v8m_mainline, - ZigLLVM_ARMSubArch_v8_1m_mainline, - ZigLLVM_ARMSubArch_v7, - ZigLLVM_ARMSubArch_v7em, - ZigLLVM_ARMSubArch_v7m, - ZigLLVM_ARMSubArch_v7s, - ZigLLVM_ARMSubArch_v7k, - ZigLLVM_ARMSubArch_v7ve, - ZigLLVM_ARMSubArch_v6, - ZigLLVM_ARMSubArch_v6m, - ZigLLVM_ARMSubArch_v6k, - ZigLLVM_ARMSubArch_v6t2, - ZigLLVM_ARMSubArch_v5, - ZigLLVM_ARMSubArch_v5te, - ZigLLVM_ARMSubArch_v4t, - - ZigLLVM_KalimbaSubArch_v3, - ZigLLVM_KalimbaSubArch_v4, - ZigLLVM_KalimbaSubArch_v5, - - ZigLLVM_MipsSubArch_r6, -}; - enum ZigLLVM_VendorType { ZigLLVM_UnknownVendor, @@ -518,7 +483,6 @@ LLVMValueRef ZigLLVMBuildAtomicRMW(LLVMBuilderRef B, enum ZigLLVM_AtomicRMWBinOp #define ZigLLVM_DIFlags_AllCallsDescribed (1U << 29) ZIG_EXTERN_C const char *ZigLLVMGetArchTypeName(enum ZigLLVM_ArchType arch); -ZIG_EXTERN_C const char *ZigLLVMGetSubArchTypeName(enum ZigLLVM_SubArchType sub_arch); ZIG_EXTERN_C const char *ZigLLVMGetVendorTypeName(enum ZigLLVM_VendorType vendor); ZIG_EXTERN_C const char *ZigLLVMGetOSTypeName(enum ZigLLVM_OSType os); ZIG_EXTERN_C const char *ZigLLVMGetEnvironmentTypeName(enum ZigLLVM_EnvironmentType abi); @@ -532,7 +496,7 @@ ZIG_EXTERN_C bool ZigLLVMWriteArchive(const char *archive_name, const char **fil bool ZigLLVMWriteImportLibrary(const char *def_path, const enum ZigLLVM_ArchType arch, const char *output_lib_path, const bool kill_at); -ZIG_EXTERN_C void ZigLLVMGetNativeTarget(enum ZigLLVM_ArchType *arch_type, enum ZigLLVM_SubArchType *sub_arch_type, +ZIG_EXTERN_C void ZigLLVMGetNativeTarget(enum ZigLLVM_ArchType *arch_type, enum ZigLLVM_VendorType *vendor_type, enum ZigLLVM_OSType *os_type, enum ZigLLVM_EnvironmentType *environ_type, enum ZigLLVM_ObjectFormatType *oformat); -- cgit v1.2.3