From 2f599b655b81004f101773b3b35dc112c0d84b72 Mon Sep 17 00:00:00 2001
From: Andrew Kelley <andrew@ziglang.org>
Date: Mon, 16 Aug 2021 01:11:10 -0700
Subject: update src/ to LLVM 13 rc1 API

---
 src/stage1/target.cpp | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'src/stage1/target.cpp')

diff --git a/src/stage1/target.cpp b/src/stage1/target.cpp
index 6594eb57d5..9c95be3d5a 100644
--- a/src/stage1/target.cpp
+++ b/src/stage1/target.cpp
@@ -25,6 +25,7 @@ static const ZigLLVM_ArchType arch_list[] = {
     ZigLLVM_bpfeb,          // eBPF or extended BPF or 64-bit BPF (big endian)
     ZigLLVM_csky,           // CSKY: csky
     ZigLLVM_hexagon,        // Hexagon: hexagon
+    ZigLLVM_m68k,           // M68k: Motorola 680x0 family
     ZigLLVM_mips,           // MIPS: mips, mipsallegrex, mipsr6
     ZigLLVM_mipsel,         // MIPSEL: mipsel, mipsallegrexe, mipsr6el
     ZigLLVM_mips64,         // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
@@ -147,6 +148,7 @@ static const ZigLLVM_EnvironmentType abi_list[] = {
     ZigLLVM_Musl,
     ZigLLVM_MuslEABI,
     ZigLLVM_MuslEABIHF,
+    ZigLLVM_MuslX32,
 
     ZigLLVM_MSVC,
     ZigLLVM_Itanium,
@@ -497,6 +499,7 @@ uint32_t target_arch_pointer_bit_width(ZigLLVM_ArchType arch) {
         case ZigLLVM_arm:
         case ZigLLVM_armeb:
         case ZigLLVM_hexagon:
+        case ZigLLVM_m68k:
         case ZigLLVM_le32:
         case ZigLLVM_mips:
         case ZigLLVM_mipsel:
@@ -564,6 +567,7 @@ uint32_t target_arch_largest_atomic_bits(ZigLLVM_ArchType arch) {
         case ZigLLVM_arm:
         case ZigLLVM_armeb:
         case ZigLLVM_hexagon:
+        case ZigLLVM_m68k:
         case ZigLLVM_le32:
         case ZigLLVM_mips:
         case ZigLLVM_mipsel:
@@ -798,6 +802,8 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
         case ZigLLVM_aarch64_32:
         case ZigLLVM_riscv32:
         case ZigLLVM_riscv64:
+        case ZigLLVM_m68k:
+        case ZigLLVM_mips:
         case ZigLLVM_mipsel:
         case ZigLLVM_ppc:
         case ZigLLVM_ppcle:
@@ -824,7 +830,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) {
         case ZigLLVM_kalimba:
         case ZigLLVM_le32:
         case ZigLLVM_le64:
-        case ZigLLVM_mips:
         case ZigLLVM_mips64:
         case ZigLLVM_mips64el:
         case ZigLLVM_msp430:
@@ -873,6 +878,7 @@ bool target_is_arm(const ZigTarget *target) {
         case ZigLLVM_bpfel:
         case ZigLLVM_csky:
         case ZigLLVM_hexagon:
+        case ZigLLVM_m68k:
         case ZigLLVM_lanai:
         case ZigLLVM_hsail:
         case ZigLLVM_hsail64:
-- 
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