From 29f41896ed9d99e82a88f4b63efa182ca0d2f93c Mon Sep 17 00:00:00 2001
From: Travis Staloch <twostepted@gmail.com>
Date: Thu, 2 Sep 2021 13:50:24 -0700
Subject: sat-arithmetic: add operator support

- adds initial support for the operators +|, -|, *|, <<|, +|=, -|=, *|=, <<|=
- uses operators in addition to builtins in behavior test
- adds binOpExt() and assignBinOpExt() to AstGen.zig. these need to be audited
---
 src/stage1/ir.cpp | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'src/stage1/ir.cpp')

diff --git a/src/stage1/ir.cpp b/src/stage1/ir.cpp
index b853961beb..2f2cfe08f3 100644
--- a/src/stage1/ir.cpp
+++ b/src/stage1/ir.cpp
@@ -9820,28 +9820,28 @@ static ErrorMsg *ir_eval_math_op_scalar(IrAnalyze *ira, Scope *scope, AstNode *s
                 float_min(out_val, op1_val, op2_val);
             }
             break;
-        case IrBinOpSatAdd:
+        case IrBinOpAddSat:
             if (is_int) {
                 bigint_add_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
             } else {
                 zig_unreachable();
             }
             break;
-        case IrBinOpSatSub:
+        case IrBinOpSubSat:
             if (is_int) {
                 bigint_sub_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
             } else {
                 zig_unreachable();
             }
             break;
-        case IrBinOpSatMul:
+        case IrBinOpMultSat:
             if (is_int) {
                 bigint_mul_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
             } else {
                 zig_unreachable();
             }
             break;
-        case IrBinOpSatShl:
+        case IrBinOpShlSat:
             if (is_int) {
                 bigint_shl_sat(&out_val->data.x_bigint, &op1_val->data.x_bigint, &op2_val->data.x_bigint, type_entry->data.integral.bit_count, type_entry->data.integral.is_signed);
             } else {
@@ -10069,10 +10069,10 @@ static bool ok_float_op(IrBinOp op) {
         case IrBinOpBitShiftRightExact:
         case IrBinOpAddWrap:
         case IrBinOpSubWrap:
-        case IrBinOpSatAdd:
-        case IrBinOpSatSub:
-        case IrBinOpSatMul:
-        case IrBinOpSatShl:
+        case IrBinOpAddSat:
+        case IrBinOpSubSat:
+        case IrBinOpMultSat:
+        case IrBinOpShlSat:
         case IrBinOpMultWrap:
         case IrBinOpArrayCat:
         case IrBinOpArrayMult:
@@ -11046,10 +11046,10 @@ static Stage1AirInst *ir_analyze_instruction_bin_op(IrAnalyze *ira, Stage1ZirIns
         case IrBinOpRemMod:
         case IrBinOpMaximum:
         case IrBinOpMinimum:
-        case IrBinOpSatAdd:
-        case IrBinOpSatSub:
-        case IrBinOpSatMul:
-        case IrBinOpSatShl:
+        case IrBinOpAddSat:
+        case IrBinOpSubSat:
+        case IrBinOpMultSat:
+        case IrBinOpShlSat:
             return ir_analyze_bin_op_math(ira, bin_op_instruction);
         case IrBinOpArrayCat:
             return ir_analyze_array_cat(ira, bin_op_instruction);
-- 
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