From df10e998ee4a935f49943fb5c0ef134f336c6ee3 Mon Sep 17 00:00:00 2001 From: Jacob G-W Date: Wed, 18 Aug 2021 21:29:32 -0400 Subject: stage2 x86_64: enable bitwise and + or and add tests --- src/codegen.zig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index d5b106dbe3..11c007dbed 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -1247,6 +1247,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { const bin_op = self.air.instructions.items(.data)[inst].bin_op; const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) { .arm, .armeb => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_and), + .x86_64 => try self.genX8664BinMath(inst, bin_op.lhs, bin_op.rhs), else => return self.fail("TODO implement bitwise and for {}", .{self.target.cpu.arch}), }; return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); @@ -1256,6 +1257,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { const bin_op = self.air.instructions.items(.data)[inst].bin_op; const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) { .arm, .armeb => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_or), + .x86_64 => try self.genX8664BinMath(inst, bin_op.lhs, bin_op.rhs), else => return self.fail("TODO implement bitwise or for {}", .{self.target.cpu.arch}), }; return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); -- cgit v1.2.3