From 4c71942f84261e9872cd27139c45b6d5fb1ab6c7 Mon Sep 17 00:00:00 2001
From: gracefu <81774659+gracefuu@users.noreply.github.com>
Date: Thu, 8 Apr 2021 05:24:17 +0800
Subject: stage2: Add .div to ir.zig

---
 src/codegen.zig | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/codegen.zig')

diff --git a/src/codegen.zig b/src/codegen.zig
index fbd412ceba..3958577d95 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -855,6 +855,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
                 .not => return self.genNot(inst.castTag(.not).?),
                 .mul => return self.genMul(inst.castTag(.mul).?),
                 .mulwrap => return self.genMulWrap(inst.castTag(.mulwrap).?),
+                .div => return self.genDiv(inst.castTag(.div).?),
                 .ptrtoint => return self.genPtrToInt(inst.castTag(.ptrtoint).?),
                 .ref => return self.genRef(inst.castTag(.ref).?),
                 .ret => return self.genRet(inst.castTag(.ret).?),
@@ -1092,6 +1093,15 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
             }
         }
 
+        fn genDiv(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
+            // No side effects, so if it's unreferenced, do nothing.
+            if (inst.base.isUnused())
+                return MCValue.dead;
+            switch (arch) {
+                else => return self.fail(inst.base.src, "TODO implement div for {}", .{self.target.cpu.arch}),
+            }
+        }
+
         fn genBitAnd(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
             // No side effects, so if it's unreferenced, do nothing.
             if (inst.base.isUnused())
-- 
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