From e878a6633f2447666217a5f9247af7c34507dca0 Mon Sep 17 00:00:00 2001 From: Meghan Denny Date: Mon, 30 Aug 2021 00:31:40 -0700 Subject: stage2: implement runtime `%` and `@rem` --- src/codegen.zig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index 9103c7ad17..a706b3b21c 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -809,6 +809,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { .mul => try self.airMul(inst), .mulwrap => try self.airMulWrap(inst), .div => try self.airDiv(inst), + .rem => try self.airRem(inst), .cmp_lt => try self.airCmp(inst, .lt), .cmp_lte => try self.airCmp(inst, .lte), @@ -1266,6 +1267,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); } + fn airRem(self: *Self, inst: Air.Inst.Index) !void { + const bin_op = self.air.instructions.items(.data)[inst].bin_op; + const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) { + else => return self.fail("TODO implement rem for {}", .{self.target.cpu.arch}), + }; + return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); + } + fn airBitAnd(self: *Self, inst: Air.Inst.Index) !void { const bin_op = self.air.instructions.items(.data)[inst].bin_op; const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (arch) { -- cgit v1.2.3