From 27c5c97f21c5e0c96d954246a6cc4d3018b71355 Mon Sep 17 00:00:00 2001 From: joachimschmidt557 Date: Sun, 15 Nov 2020 20:55:57 +0100 Subject: stage2 ARM: genAdd, genSub for simple cases --- src/codegen.zig | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index 74800aa22e..3242dcd0b0 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -987,6 +987,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { .x86_64 => { return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 0, 0x00); }, + .arm, .armeb => return try self.genArmBinArith(inst, .add), else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}), } } @@ -1144,10 +1145,99 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { .x86_64 => { return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 5, 0x28); }, + .arm, .armeb => return try self.genArmBinArith(inst, .sub), else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}), } } + fn genArmBinArith(self: *Self, inst: *ir.Inst.BinOp, op: ir.Inst.Tag) !MCValue { + const lhs = try self.resolveInst(inst.lhs); + const rhs = try self.resolveInst(inst.rhs); + + // Destination must be a register + // Source may be register, memory or an immediate + // + // So there are two options: (lhs is src and rhs is dest) + // or (rhs is src and lhs is dest) + const lhs_is_dest = blk: { + if (self.reuseOperand(&inst.base, 0, lhs)) { + break :blk true; + } else if (self.reuseOperand(&inst.base, 1, rhs)) { + break :blk false; + } else { + break :blk lhs == .register; + } + }; + + var dst_mcv: MCValue = undefined; + var src_mcv: MCValue = undefined; + var src_inst: *ir.Inst = undefined; + if (lhs_is_dest) { + // LHS is the destination + // RHS is the source + src_inst = inst.rhs; + src_mcv = rhs; + dst_mcv = if (lhs != .register) try self.copyToNewRegister(&inst.base, lhs) else lhs; + } else { + // RHS is the destination + // LHS is the source + src_inst = inst.lhs; + src_mcv = lhs; + dst_mcv = if (rhs != .register) try self.copyToNewRegister(&inst.base, rhs) else rhs; + } + + try self.genArmBinArithCode(inst.base.src, dst_mcv.register, src_mcv, lhs_is_dest, op); + return dst_mcv; + } + + fn genArmBinArithCode( + self: *Self, + src: usize, + dst_reg: Register, + src_mcv: MCValue, + lhs_is_dest: bool, + op: ir.Inst.Tag, + ) !void { + const operand = switch (src_mcv) { + .none => unreachable, + .undef => unreachable, + .dead, .unreach => unreachable, + .compare_flags_unsigned => unreachable, + .compare_flags_signed => unreachable, + .ptr_stack_offset => unreachable, + .ptr_embedded_in_code => unreachable, + .immediate => |imm| blk: { + if (imm > std.math.maxInt(u32)) return self.fail(src, "TODO ARM binary arithmetic immediate larger than u32", .{}); + + // Load immediate into register if it doesn't fit + // as an operand + break :blk Instruction.Operand.fromU32(@intCast(u32, imm)) orelse + Instruction.Operand.reg(try self.copyToTmpRegister(src, src_mcv), Instruction.Operand.Shift.none); + }, + .register => |src_reg| Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none), + .stack_offset, + .embedded_in_code, + .memory, + => Instruction.Operand.reg(try self.copyToTmpRegister(src, src_mcv), Instruction.Operand.Shift.none), + }; + + switch (op) { + .add => { + // TODO runtime safety checks (overflow) + writeInt(u32, try self.code.addManyAsArray(4), Instruction.add(.al, dst_reg, dst_reg, operand).toU32()); + }, + .sub => { + // TODO runtime safety checks (underflow) + if (lhs_is_dest) { + writeInt(u32, try self.code.addManyAsArray(4), Instruction.sub(.al, dst_reg, dst_reg, operand).toU32()); + } else { + writeInt(u32, try self.code.addManyAsArray(4), Instruction.rsb(.al, dst_reg, dst_reg, operand).toU32()); + } + }, + else => unreachable, // not a binary arithmetic instruction + } + } + /// ADD, SUB, XOR, OR, AND fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue { try self.code.ensureCapacity(self.code.items.len + 8); @@ -2106,7 +2196,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { // lhs OR rhs return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08); }, - else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}), + else => return self.fail(inst.base.src, "TODO implement boolean operations for {}", .{self.target.cpu.arch}), } } -- cgit v1.2.3 From 85a3991a4392cee42acf0ed5fed185afdc2b133c Mon Sep 17 00:00:00 2001 From: joachimschmidt557 Date: Sat, 21 Nov 2020 19:15:01 +0100 Subject: stage2 codegen: use switch in genBoolOp --- src/codegen.zig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index 3242dcd0b0..bec188cc5c 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -2189,12 +2189,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { if (inst.base.isUnused()) return MCValue.dead; switch (arch) { - .x86_64 => if (inst.base.tag == .booland) { + .x86_64 => switch (inst.base.tag) { // lhs AND rhs - return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20); - } else { + .booland => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20), // lhs OR rhs - return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08); + .boolor => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08), + else => unreachable, }, else => return self.fail(inst.base.src, "TODO implement boolean operations for {}", .{self.target.cpu.arch}), } -- cgit v1.2.3 From f06f0ebcda57c65f481e5da41fb3949b9863744c Mon Sep 17 00:00:00 2001 From: joachimschmidt557 Date: Sun, 22 Nov 2020 22:13:17 +0100 Subject: stage2 ARM: Implement genNot --- src/codegen.zig | 43 +++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index bec188cc5c..329bacdabf 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -975,6 +975,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { }; return try self.genX8664BinMath(&inst.base, inst.operand, &imm.base, 6, 0x30); }, + .arm, .armeb => { + var imm = ir.Inst.Constant{ + .base = .{ + .tag = .constant, + .deaths = 0, + .ty = inst.operand.ty, + .src = inst.operand.src, + }, + .val = Value.initTag(.bool_true), + }; + return try self.genArmBinOp(&inst.base, inst.operand, &imm.base, .not); + }, else => return self.fail(inst.base.src, "TODO implement NOT for {}", .{self.target.cpu.arch}), } } @@ -987,7 +999,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { .x86_64 => { return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 0, 0x00); }, - .arm, .armeb => return try self.genArmBinArith(inst, .add), + .arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .add), else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}), } } @@ -1145,14 +1157,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { .x86_64 => { return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 5, 0x28); }, - .arm, .armeb => return try self.genArmBinArith(inst, .sub), + .arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .sub), else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}), } } - fn genArmBinArith(self: *Self, inst: *ir.Inst.BinOp, op: ir.Inst.Tag) !MCValue { - const lhs = try self.resolveInst(inst.lhs); - const rhs = try self.resolveInst(inst.rhs); + fn genArmBinOp(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, op: ir.Inst.Tag) !MCValue { + const lhs = try self.resolveInst(op_lhs); + const rhs = try self.resolveInst(op_rhs); // Destination must be a register // Source may be register, memory or an immediate @@ -1160,9 +1172,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { // So there are two options: (lhs is src and rhs is dest) // or (rhs is src and lhs is dest) const lhs_is_dest = blk: { - if (self.reuseOperand(&inst.base, 0, lhs)) { + if (self.reuseOperand(inst, 0, lhs)) { break :blk true; - } else if (self.reuseOperand(&inst.base, 1, rhs)) { + } else if (self.reuseOperand(inst, 1, rhs)) { break :blk false; } else { break :blk lhs == .register; @@ -1175,22 +1187,22 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { if (lhs_is_dest) { // LHS is the destination // RHS is the source - src_inst = inst.rhs; + src_inst = op_rhs; src_mcv = rhs; - dst_mcv = if (lhs != .register) try self.copyToNewRegister(&inst.base, lhs) else lhs; + dst_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs; } else { // RHS is the destination // LHS is the source - src_inst = inst.lhs; + src_inst = op_lhs; src_mcv = lhs; - dst_mcv = if (rhs != .register) try self.copyToNewRegister(&inst.base, rhs) else rhs; + dst_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs; } - try self.genArmBinArithCode(inst.base.src, dst_mcv.register, src_mcv, lhs_is_dest, op); + try self.genArmBinOpCode(inst.src, dst_mcv.register, src_mcv, lhs_is_dest, op); return dst_mcv; } - fn genArmBinArithCode( + fn genArmBinOpCode( self: *Self, src: usize, dst_reg: Register, @@ -1234,7 +1246,10 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { writeInt(u32, try self.code.addManyAsArray(4), Instruction.rsb(.al, dst_reg, dst_reg, operand).toU32()); } }, - else => unreachable, // not a binary arithmetic instruction + .not => { + writeInt(u32, try self.code.addManyAsArray(4), Instruction.eor(.al, dst_reg, dst_reg, operand).toU32()); + }, + else => unreachable, // not a binary instruction } } -- cgit v1.2.3 From 2ad263658872a7b8b7bf3275c35d0e4c4faebccd Mon Sep 17 00:00:00 2001 From: joachimschmidt557 Date: Tue, 24 Nov 2020 22:32:36 +0100 Subject: stage2 ARM: use strb + implement genBoolOp --- src/codegen.zig | 61 +++++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 15 deletions(-) (limited to 'src/codegen.zig') diff --git a/src/codegen.zig b/src/codegen.zig index 329bacdabf..ee3f0ee4a8 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -1246,6 +1246,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { writeInt(u32, try self.code.addManyAsArray(4), Instruction.rsb(.al, dst_reg, dst_reg, operand).toU32()); } }, + .booland => { + writeInt(u32, try self.code.addManyAsArray(4), Instruction.@"and"(.al, dst_reg, dst_reg, operand).toU32()); + }, + .boolor => { + writeInt(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, dst_reg, dst_reg, operand).toU32()); + }, .not => { writeInt(u32, try self.code.addManyAsArray(4), Instruction.eor(.al, dst_reg, dst_reg, operand).toU32()); }, @@ -2209,7 +2215,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { .booland => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20), // lhs OR rhs .boolor => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08), - else => unreachable, + else => unreachable, // Not a boolean operation + }, + .arm, .armeb => switch (inst.base.tag) { + .booland => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .booland), + .boolor => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .boolor), + else => unreachable, // Not a boolean operation }, else => return self.fail(inst.base.src, "TODO implement boolean operations for {}", .{self.target.cpu.arch}), } @@ -2464,14 +2475,23 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { return self.fail(src, "TODO implement set stack variable from embedded_in_code", .{}); }, .register => |reg| { - // TODO: strb, strh - if (stack_offset <= math.maxInt(u12)) { - writeInt(u32, try self.code.addManyAsArray(4), Instruction.str(.al, reg, .fp, .{ - .offset = Instruction.Offset.imm(@intCast(u12, stack_offset)), + // TODO: strh + const offset = if (stack_offset <= math.maxInt(u12)) blk: { + break :blk Instruction.Offset.imm(@intCast(u12, stack_offset)); + } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = stack_offset }), 0); + + const abi_size = ty.abiSize(self.target.*); + switch (abi_size) { + 1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.strb(.al, reg, .fp, .{ + .offset = offset, .positive = false, - }).toU32()); - } else { - return self.fail(src, "TODO genSetStack with larger offsets", .{}); + }).toU32()), + 2 => return self.fail(src, "TODO implement strh", .{}), + 4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.str(.al, reg, .fp, .{ + .offset = offset, + .positive = false, + }).toU32()), + else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}), } }, .memory => |vaddr| { @@ -2642,15 +2662,26 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, .{ .offset = Instruction.Offset.none }).toU32()); }, .stack_offset => |unadjusted_off| { - // TODO: ldrb, ldrh + // TODO: ldrh // TODO: maybe addressing from sp instead of fp - if (unadjusted_off <= math.maxInt(u12)) { - writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, .fp, .{ - .offset = Instruction.Offset.imm(@intCast(u12, unadjusted_off)), + const offset = if (unadjusted_off <= math.maxInt(u12)) blk: { + break :blk Instruction.Offset.imm(@intCast(u12, unadjusted_off)); + } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = unadjusted_off }), 0); + + // TODO: supply type information to genSetReg as we do to genSetStack + // const abi_size = ty.abiSize(self.target.*); + const abi_size = 4; + switch (abi_size) { + 1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldrb(.al, reg, .fp, .{ + .offset = offset, .positive = false, - }).toU32()); - } else { - return self.fail(src, "TODO genSetReg with larger stack offset", .{}); + }).toU32()), + 2 => return self.fail(src, "TODO implement strh", .{}), + 4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, .fp, .{ + .offset = offset, + .positive = false, + }).toU32()), + else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}), } }, else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}), -- cgit v1.2.3