From 11998d2972bf1f7253351fc756c4f1766a412f1d Mon Sep 17 00:00:00 2001
From: Vexu <git@vexu.eu>
Date: Mon, 12 Oct 2020 15:35:48 +0300
Subject: stage2: basic switch analysis

---
 src/codegen.zig | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/codegen.zig')

diff --git a/src/codegen.zig b/src/codegen.zig
index 5e5215c992..9deeab82a5 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -786,6 +786,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
                 .unwrap_optional => return self.genUnwrapOptional(inst.castTag(.unwrap_optional).?),
                 .wrap_optional => return self.genWrapOptional(inst.castTag(.wrap_optional).?),
                 .varptr => return self.genVarPtr(inst.castTag(.varptr).?),
+                .@"switch" => return self.genSwitch(inst.castTag(.@"switch").?),
             }
         }
 
@@ -1989,6 +1990,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
             return @bitCast(MCValue, inst.codegen.mcv);
         }
 
+        fn genSwitch(self: *Self, inst: *ir.Inst.Switch) !MCValue {
+            switch (arch) {
+                else => return self.fail(inst.base.src, "TODO genSwitch for {}", .{self.target.cpu.arch}),
+            }
+        }
+
         fn performReloc(self: *Self, src: usize, reloc: Reloc) !void {
             switch (reloc) {
                 .rel32 => |pos| {
-- 
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