From afbf99c84671992acb4129a6a7bc70d604c4d00d Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Thu, 18 Jul 2019 12:28:24 -0400 Subject: riscv musl: only add the +a feature --- src/codegen.cpp | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'src/codegen.cpp') diff --git a/src/codegen.cpp b/src/codegen.cpp index 7136429615..2c5f2c96e5 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -8409,16 +8409,11 @@ void add_cc_args(CodeGen *g, ZigList &args, const char *out_dep_pa if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) { // Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's // cross compilation CPU info for RISCV. - switch (g->zig_target->arch) { - case ZigLLVM_riscv32: - args.append("-march=rv32ia"); - break; - case ZigLLVM_riscv64: - args.append("-march=rv64ia"); - break; - default: - zig_unreachable(); - } + // TODO: https://github.com/ziglang/zig/issues/2883 + args.append("-Xclang"); + args.append("-target-feature"); + args.append("-Xclang"); + args.append("+a"); } } if (g->zig_target->os == OsFreestanding) { -- cgit v1.2.3