From 7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2 Mon Sep 17 00:00:00 2001
From: joachimschmidt557 <joachim.schmidt557@outlook.com>
Date: Sat, 19 Mar 2022 19:48:27 +0100
Subject: stage2 RISCV64: implement move register to register

---
 src/arch/riscv64/CodeGen.zig | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/arch/riscv64/CodeGen.zig')

diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
index 65983a5661..36c1752e5d 100644
--- a/src/arch/riscv64/CodeGen.zig
+++ b/src/arch/riscv64/CodeGen.zig
@@ -2074,6 +2074,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
                 return self.fail("TODO genSetReg 33-64 bit immediates for riscv64", .{}); // glhf
             }
         },
+        .register => |src_reg| {
+            // If the registers are the same, nothing to do.
+            if (src_reg.id() == reg.id())
+                return;
+
+            // mov reg, src_reg
+            _ = try self.addInst(.{
+                .tag = .mv,
+                .data = .{ .rr = .{
+                    .rd = reg,
+                    .rs = src_reg,
+                } },
+            });
+        },
         .memory => |addr| {
             // The value is in memory at a hard-coded address.
             // If the type is a pointer, it means the pointer address is at this memory location.
-- 
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