From 558b4ac1f0fd7123ebe25f3e59eef275b066c50a Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Wed, 18 Sep 2019 10:24:28 -0400 Subject: adjust codegen of casting between arrays and vectors * bitcasting is still better when the size_in_bits aligns with the ABI size of the element type. Logic is reworked to do bitcasting when possible * rather than using insertelement/extractelement to work with arrays, store/load elements directly. This matches codegen for arrays elsewhere. --- src/all_types.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/all_types.hpp') diff --git a/src/all_types.hpp b/src/all_types.hpp index 60b292662d..e682eb8de1 100644 --- a/src/all_types.hpp +++ b/src/all_types.hpp @@ -1351,7 +1351,7 @@ struct ZigTypeBoundFn { }; struct ZigTypeVector { - // The type must be a pointer, integer, or float + // The type must be a pointer, integer, bool, or float ZigType *elem_type; uint32_t len; }; -- cgit v1.2.3 From 193604c837df75ab0c3fa5860f8b234263fe5b50 Mon Sep 17 00:00:00 2001 From: Shawn Landden Date: Sat, 29 Jun 2019 11:32:26 -0500 Subject: stage1: add @shuffle() shufflevector support I change the semantics of the mask operand, to make it a little more flexible. There is no real danger in this because it is a compile-error if you do it the LLVM way (and there is an appropiate error to tell you this). v2: avoid problems with double-free --- doc/langref.html.in | 22 ++++ src/all_types.hpp | 11 ++ src/codegen.cpp | 32 +++++ src/ir.cpp | 274 +++++++++++++++++++++++++++++++++++++++ src/ir_print.cpp | 17 +++ test/compile_errors.zig | 13 ++ test/stage1/behavior/shuffle.zig | 57 ++++++++ 7 files changed, 426 insertions(+) create mode 100644 test/stage1/behavior/shuffle.zig (limited to 'src/all_types.hpp') diff --git a/doc/langref.html.in b/doc/langref.html.in index 374fbfcde5..7ae0ee7c1c 100644 --- a/doc/langref.html.in +++ b/doc/langref.html.in @@ -8226,6 +8226,28 @@ fn foo(comptime T: type, ptr: *T) T { {#link|pointer|Pointers#}.

{#header_close#} + + {#header_open|@shuffle#} + 
{#syntax#}@shuffle(comptime ElemType: type, a: @Vector(_, ElemType), b: @Vector(_, ElemType), comptime mask: @Vector(_, u32)) @Vector(mask.len, ElemType){#endsyntax#}
+

+ Does the {#syntax#}shufflevector{#endsyntax#} instruction. Each element in {#syntax#}comptime{#endsyntax#} + (and always {#syntax#}i32{#endsyntax#}) {#syntax#}mask{#endsyntax#} selects a element from either {#syntax#}a{#endsyntax#} or {#syntax#}b{#endsyntax#}. + Positive numbers select from {#syntax#}a{#endsyntax#} (starting at 0), while negative values select + from {#syntax#}b{#endsyntax#} (starting at -1 and going down). It is recommended to use the {#syntax#}~{#endsyntax#} + operator from indexes from b so that both indexes can start from 0 (i.e. ~0 is -1). If either the {#syntax#}mask{#endsyntax#} + value or the value from {#syntax#}a{#endsyntax#} or {#syntax#}b{#endsyntax#} that it selects are {#syntax#}undefined{#endsyntax#} + then the resulting value is {#syntax#}undefined{#endsyntax#}. Also see {#link|SIMD#} and + the relevent LLVM Documentation on + {#syntax#}shufflevector{#endsyntax#}, although note that the mask values are interpreted differently than in LLVM-IR. + Also, unlike LLVM-IR, the number of elements in {#syntax#}a{#endsyntax#} and {#syntax#}b{#endsyntax#} do not have to match. + The {#syntax#}undefined{#endsyntax#} identifier can be selected from up to the length of the other vector, + and yields {#syntax#}undefined{#endsyntax#}. If both vectors are {#syntax#}undefined{#endsyntax#}, yields an + {#syntax#}undefined{#endsyntax#} {#syntax#}ElemType{#endsyntax#} vector with length of {#syntax#}mask{#endsyntax#}.

+

+ {#syntax#}ElemType{#endsyntax#} must be an {#link|integer|Integers#}, a {#link|float|Floats#}, or a + {#link|pointer|Pointers#}. The mask may be any vector length that the target supports, and its' length determines the result length. +

+ {#header_close#} {#header_close#} {#header_open|Build Mode#} diff --git a/src/all_types.hpp b/src/all_types.hpp index e682eb8de1..deb56cbb40 100644 --- a/src/all_types.hpp +++ b/src/all_types.hpp @@ -1611,6 +1611,7 @@ enum BuiltinFnId { BuiltinFnIdIntToEnum, BuiltinFnIdIntType, BuiltinFnIdVectorType, + BuiltinFnIdShuffle, BuiltinFnIdSetCold, BuiltinFnIdSetRuntimeSafety, BuiltinFnIdSetFloatMode, @@ -2428,6 +2429,7 @@ enum IrInstructionId { IrInstructionIdBoolToInt, IrInstructionIdIntType, IrInstructionIdVectorType, + IrInstructionIdShuffleVector, IrInstructionIdBoolNot, IrInstructionIdMemset, IrInstructionIdMemcpy, @@ -3669,6 +3671,15 @@ struct IrInstructionVectorToArray { IrInstruction *result_loc; }; +struct IrInstructionShuffleVector { + IrInstruction base; + + IrInstruction *scalar_type; + IrInstruction *a; + IrInstruction *b; + IrInstruction *mask; // This is in zig-format, not llvm format +}; + struct IrInstructionAssertZero { IrInstruction base; diff --git a/src/codegen.cpp b/src/codegen.cpp index e4b47be8e5..2f1488635a 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -4581,6 +4581,35 @@ static LLVMValueRef ir_render_ctz(CodeGen *g, IrExecutable *executable, IrInstru return gen_widen_or_shorten(g, false, int_type, instruction->base.value.type, wrong_size_int); } +static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, IrExecutable *executable, IrInstructionShuffleVector *instruction) { + uint64_t len_a = instruction->a->value.type->data.vector.len; + uint64_t len_c = instruction->mask->value.type->data.vector.len; + + // LLVM uses integers larger than the length of the first array to + // index into the second array. This was deemed unnecessarily fragile + // when changing code, so Zig uses negative numbers to index the + // second vector. These start at -1 and go down, and are easiest to use + // with the ~ operator. Here we convert between the two formats. + IrInstruction *mask = instruction->mask; + LLVMValueRef *values = allocate(len_c); + for (uint64_t i = 0;i < len_c;i++) { + if (mask->value.data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) { + values[i] = LLVMGetUndef(LLVMInt32Type()); + } else { + int64_t v = bigint_as_signed(&mask->value.data.x_array.data.s_none.elements[i].data.x_bigint); + if (v < 0) + v = (uint32_t)~v + (uint32_t)len_a; + values[i] = LLVMConstInt(LLVMInt32Type(), v, false); + } + } + + return LLVMBuildShuffleVector(g->builder, + ir_llvm_value(g, instruction->a), + ir_llvm_value(g, instruction->b), + LLVMConstVector(values, len_c), + ""); +} + static LLVMValueRef ir_render_pop_count(CodeGen *g, IrExecutable *executable, IrInstructionPopCount *instruction) { ZigType *int_type = instruction->op->value.type; LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdPopCount); @@ -6095,6 +6124,8 @@ static LLVMValueRef ir_render_instruction(CodeGen *g, IrExecutable *executable, return ir_render_spill_begin(g, executable, (IrInstructionSpillBegin *)instruction); case IrInstructionIdSpillEnd: return ir_render_spill_end(g, executable, (IrInstructionSpillEnd *)instruction); + case IrInstructionIdShuffleVector: + return ir_render_shuffle_vector(g, executable, (IrInstructionShuffleVector *) instruction); } zig_unreachable(); } @@ -7785,6 +7816,7 @@ static void define_builtin_fns(CodeGen *g) { create_builtin_fn(g, BuiltinFnIdCompileLog, "compileLog", SIZE_MAX); create_builtin_fn(g, BuiltinFnIdIntType, "IntType", 2); // TODO rename to Int create_builtin_fn(g, BuiltinFnIdVectorType, "Vector", 2); + create_builtin_fn(g, BuiltinFnIdShuffle, "shuffle", 4); create_builtin_fn(g, BuiltinFnIdSetCold, "setCold", 1); create_builtin_fn(g, BuiltinFnIdSetRuntimeSafety, "setRuntimeSafety", 1); create_builtin_fn(g, BuiltinFnIdSetFloatMode, "setFloatMode", 1); diff --git a/src/ir.cpp b/src/ir.cpp index 6de08de913..f62a58e37e 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -717,6 +717,10 @@ static constexpr IrInstructionId ir_instruction_id(IrInstructionVectorType *) { return IrInstructionIdVectorType; } +static constexpr IrInstructionId ir_instruction_id(IrInstructionShuffleVector *) { + return IrInstructionIdShuffleVector; +} + static constexpr IrInstructionId ir_instruction_id(IrInstructionBoolNot *) { return IrInstructionIdBoolNot; } @@ -2277,6 +2281,25 @@ static IrInstruction *ir_build_vector_type(IrBuilder *irb, Scope *scope, AstNode return &instruction->base; } +static IrInstruction *ir_build_shuffle_vector(IrBuilder *irb, Scope *scope, AstNode *source_node, + IrInstruction *scalar_type, IrInstruction *a, IrInstruction *b, IrInstruction *mask) +{ + IrInstructionShuffleVector *instruction = ir_build_instruction(irb, scope, source_node); + instruction->scalar_type = scalar_type; + instruction->a = a; + instruction->b = b; + instruction->mask = mask; + + if (scalar_type != nullptr) { + ir_ref_instruction(scalar_type, irb->current_basic_block); + } + ir_ref_instruction(a, irb->current_basic_block); + ir_ref_instruction(b, irb->current_basic_block); + ir_ref_instruction(mask, irb->current_basic_block); + + return &instruction->base; +} + static IrInstruction *ir_build_bool_not(IrBuilder *irb, Scope *scope, AstNode *source_node, IrInstruction *value) { IrInstructionBoolNot *instruction = ir_build_instruction(irb, scope, source_node); instruction->value = value; @@ -4936,6 +4959,32 @@ static IrInstruction *ir_gen_builtin_fn_call(IrBuilder *irb, Scope *scope, AstNo IrInstruction *vector_type = ir_build_vector_type(irb, scope, node, arg0_value, arg1_value); return ir_lval_wrap(irb, scope, vector_type, lval, result_loc); } + case BuiltinFnIdShuffle: + { + AstNode *arg0_node = node->data.fn_call_expr.params.at(0); + IrInstruction *arg0_value = ir_gen_node(irb, arg0_node, scope); + if (arg0_value == irb->codegen->invalid_instruction) + return arg0_value; + + AstNode *arg1_node = node->data.fn_call_expr.params.at(1); + IrInstruction *arg1_value = ir_gen_node(irb, arg1_node, scope); + if (arg1_value == irb->codegen->invalid_instruction) + return arg1_value; + + AstNode *arg2_node = node->data.fn_call_expr.params.at(2); + IrInstruction *arg2_value = ir_gen_node(irb, arg2_node, scope); + if (arg2_value == irb->codegen->invalid_instruction) + return arg2_value; + + AstNode *arg3_node = node->data.fn_call_expr.params.at(3); + IrInstruction *arg3_value = ir_gen_node(irb, arg3_node, scope); + if (arg3_value == irb->codegen->invalid_instruction) + return arg3_value; + + IrInstruction *shuffle_vector = ir_build_shuffle_vector(irb, scope, node, + arg0_value, arg1_value, arg2_value, arg3_value); + return ir_lval_wrap(irb, scope, shuffle_vector, lval, result_loc); + } case BuiltinFnIdMemcpy: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); @@ -22063,6 +22112,228 @@ static IrInstruction *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstr return ir_const_type(ira, &instruction->base, vector_type); } +static IrInstruction *ir_analyze_shuffle_vector(IrAnalyze *ira, IrInstruction *source_instr, + ZigType *scalar_type, IrInstruction *a, IrInstruction *b, IrInstruction *mask) { + assert(source_instr && scalar_type && a && b && mask); + assert(scalar_type->id == ZigTypeIdBool || + scalar_type->id == ZigTypeIdInt || + scalar_type->id == ZigTypeIdFloat || + scalar_type->id == ZigTypeIdPointer); + + ZigType *mask_type = mask->value.type; + if (type_is_invalid(mask_type)) + return ira->codegen->invalid_instruction; + + const char *shuffle_mask_fail_fmt = "@shuffle mask operand must be a vector of signed 32-bit integers, got '%s'"; + + if (mask_type->id == ZigTypeIdArray) { + ZigType *vector_type = get_vector_type(ira->codegen, mask_type->data.array.len, mask_type->data.array.child_type); + mask = ir_analyze_array_to_vector(ira, mask, mask, vector_type); + if (!mask) + return ira->codegen->invalid_instruction; + mask_type = vector_type; + } + + if (mask_type->id != ZigTypeIdVector) { + ir_add_error(ira, mask, + buf_sprintf(shuffle_mask_fail_fmt, buf_ptr(&mask->value.type->name))); + return ira->codegen->invalid_instruction; + } + + ZigType *mask_scalar_type = mask_type->data.array.child_type; + if (mask_scalar_type->id != ZigTypeIdInt) { + ir_add_error(ira, mask, + buf_sprintf(shuffle_mask_fail_fmt, buf_ptr(&mask->value.type->name))); + return ira->codegen->invalid_instruction; + } + + if (mask_scalar_type->data.integral.bit_count != 32 || + mask_scalar_type->data.integral.is_signed == false) { + ir_add_error(ira, mask, + buf_sprintf(shuffle_mask_fail_fmt, buf_ptr(&mask->value.type->name))); + return ira->codegen->invalid_instruction; + } + + uint64_t len_a, len_b, len_c = mask->value.type->data.vector.len; + if (a->value.type->id != ZigTypeIdVector) { + if (a->value.type->id != ZigTypeIdUndefined) { + ir_add_error(ira, a, + buf_sprintf("expected vector of element type '%s' got '%s'", + buf_ptr(&scalar_type->name), + buf_ptr(&a->value.type->name))); + return ira->codegen->invalid_instruction; + } + } else { + len_a = a->value.type->data.vector.len; + } + + if (b->value.type->id != ZigTypeIdVector) { + if (b->value.type->id != ZigTypeIdUndefined) { + ir_add_error(ira, b, + buf_sprintf("expected vector of element type '%s' got '%s'", + buf_ptr(&scalar_type->name), + buf_ptr(&b->value.type->name))); + return ira->codegen->invalid_instruction; + } + } else { + len_b = b->value.type->data.vector.len; + } + + if (a->value.type->id == ZigTypeIdUndefined && b->value.type->id == ZigTypeIdUndefined) { + return ir_const_undef(ira, a, get_vector_type(ira->codegen, len_c, scalar_type)); + } + + // undefined is a vector up to length of the other vector. + if (a->value.type->id == ZigTypeIdUndefined) { + a = ir_const_undef(ira, a, b->value.type); + len_a = b->value.type->data.vector.len; + } else if (b->value.type->id == ZigTypeIdUndefined) { + b = ir_const_undef(ira, b, a->value.type); + len_b = a->value.type->data.vector.len; + } + + // FIXME I think this needs to be more sophisticated + if (a->value.type->data.vector.elem_type != scalar_type) { + ir_add_error(ira, a, + buf_sprintf("element type '%s' does not match '%s'", + buf_ptr(&a->value.type->data.vector.elem_type->name), + buf_ptr(&scalar_type->name))); + return ira->codegen->invalid_instruction; + } + if (b->value.type->data.vector.elem_type != scalar_type) { + ir_add_error(ira, b, + buf_sprintf("element type '%s' does not match '%s'", + buf_ptr(&b->value.type->data.vector.elem_type->name), + buf_ptr(&scalar_type->name))); + return ira->codegen->invalid_instruction; + } + + if (a->value.type != b->value.type) { + assert(len_a != len_b); + uint32_t len_max = max(len_a, len_b), len_min = min(len_a, len_b); + bool expand_b = len_b < len_a; + IrInstruction *expand_mask = ir_const(ira, mask, + get_vector_type(ira->codegen, len_max, ira->codegen->builtin_types.entry_i32)); + expand_mask->value.data.x_array.data.s_none.elements = create_const_vals(len_max); + uint32_t i = 0; + for (; i < len_min; i++) + bigint_init_unsigned(&expand_mask->value.data.x_array.data.s_none.elements[i].data.x_bigint, i); + for (; i < len_max; i++) + bigint_init_signed(&expand_mask->value.data.x_array.data.s_none.elements[i].data.x_bigint, -1); + IrInstruction *undef = ir_const_undef(ira, source_instr, + get_vector_type(ira->codegen, len_min, scalar_type)); + if (expand_b) { + if (instr_is_comptime(b)) { + ConstExprValue *old = b->value.data.x_array.data.s_none.elements; + b->value.data.x_array.data.s_none.elements = + allocate(len_a); + memcpy(b->value.data.x_array.data.s_none.elements, old, + b->value.type->data.vector.len * sizeof(ConstExprValue)); + } else { + b = ir_build_shuffle_vector(&ira->new_irb, + source_instr->scope, source_instr->source_node, + nullptr, b, undef, expand_mask); + b->value.special = ConstValSpecialRuntime; + } + b->value.type = get_vector_type(ira->codegen, len_max, scalar_type); + } else { + if (instr_is_comptime(a)) { + ConstExprValue *old = a->value.data.x_array.data.s_none.elements; + a->value.data.x_array.data.s_none.elements = + allocate(len_b); + memcpy(a->value.data.x_array.data.s_none.elements, old, + a->value.type->data.vector.len * sizeof(ConstExprValue)); + } else { + a = ir_build_shuffle_vector(&ira->new_irb, + source_instr->scope, source_instr->source_node, + nullptr, a, undef, expand_mask); + a->value.special = ConstValSpecialRuntime; + } + a->value.type = get_vector_type(ira->codegen, len_max, scalar_type); + } + } + ConstExprValue *mask_val = ir_resolve_const(ira, mask, UndefOk); + if (!mask_val) { + ir_add_error(ira, mask, + buf_sprintf("mask must be comptime")); + return ira->codegen->invalid_instruction; + } + for (uint32_t i = 0;i < mask->value.type->data.vector.len;i++) { + if (mask->value.data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) + continue; + int64_t v = bigint_as_signed(&mask->value.data.x_array.data.s_none.elements[i].data.x_bigint); + if (v >= 0 && (uint64_t)v + 1 > len_a) { + ErrorMsg *msg = ir_add_error(ira, mask, + buf_sprintf("mask index out of bounds")); + add_error_note(ira->codegen, msg, mask->source_node, + buf_sprintf("when computing vector element at index %" ZIG_PRI_usize, (uintptr_t)i)); + if ((uint64_t)v <= len_a + len_b) + add_error_note(ira->codegen, msg, mask->source_node, + buf_sprintf("selections from the second vector are specified with negative numbers")); + } else if (v < 0 && (uint64_t)~v + 1 > len_b) { + ErrorMsg *msg = ir_add_error(ira, mask, + buf_sprintf("mask index out of bounds")); + add_error_note(ira->codegen, msg, mask->source_node, + buf_sprintf("when computing vector element at index %" ZIG_PRI_usize, (uintptr_t)i)); + } + else + continue; + return ira->codegen->invalid_instruction; + } + + ZigType *result_type = get_vector_type(ira->codegen, len_c, scalar_type); + if (instr_is_comptime(a) && + instr_is_comptime(b)) { + IrInstruction *result = ir_const(ira, source_instr, result_type); + result->value.data.x_array.data.s_none.elements = create_const_vals(len_c); + for (uint32_t i = 0;i < mask->value.type->data.vector.len;i++) { + if (mask->value.data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) + result->value.data.x_array.data.s_none.elements[i].special = + ConstValSpecialUndef; + int64_t v = bigint_as_signed(&mask->value.data.x_array.data.s_none.elements[i].data.x_bigint); + if (v >= 0) + result->value.data.x_array.data.s_none.elements[i] = + a->value.data.x_array.data.s_none.elements[v]; + else if (v < 0) + result->value.data.x_array.data.s_none.elements[i] = + b->value.data.x_array.data.s_none.elements[~v]; + else + zig_unreachable(); + result->value.data.x_array.data.s_none.elements[i].special = + ConstValSpecialStatic; + } + result->value.special = ConstValSpecialStatic; + return result; + } + + // All static analysis passed, and not comptime + IrInstruction *result = ir_build_shuffle_vector(&ira->new_irb, + source_instr->scope, source_instr->source_node, + nullptr, a, b, mask); + result->value.type = result_type; + result->value.special = ConstValSpecialRuntime; + return result; +} + +static IrInstruction *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, IrInstructionShuffleVector *instruction) { + ZigType *scalar_type = ir_resolve_type(ira, instruction->scalar_type); + assert(scalar_type); + if (type_is_invalid(scalar_type)) + return ira->codegen->invalid_instruction; + + if (scalar_type->id != ZigTypeIdBool && + scalar_type->id != ZigTypeIdInt && + scalar_type->id != ZigTypeIdFloat && + scalar_type->id != ZigTypeIdPointer) { + ir_add_error(ira, instruction->scalar_type, + buf_sprintf("vector element type must be integer, float, bool, or pointer; '%s' is invalid", + buf_ptr(&scalar_type->name))); + return ira->codegen->invalid_instruction; + } + + return ir_analyze_shuffle_vector(ira, &instruction->base, scalar_type, instruction->a->child, instruction->b->child, instruction->mask->child); +} + static IrInstruction *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstructionBoolNot *instruction) { IrInstruction *value = instruction->value->child; if (type_is_invalid(value->value.type)) @@ -25607,6 +25878,8 @@ static IrInstruction *ir_analyze_instruction_base(IrAnalyze *ira, IrInstruction return ir_analyze_instruction_int_type(ira, (IrInstructionIntType *)instruction); case IrInstructionIdVectorType: return ir_analyze_instruction_vector_type(ira, (IrInstructionVectorType *)instruction); + case IrInstructionIdShuffleVector: + return ir_analyze_instruction_shuffle_vector(ira, (IrInstructionShuffleVector *)instruction); case IrInstructionIdBoolNot: return ir_analyze_instruction_bool_not(ira, (IrInstructionBoolNot *)instruction); case IrInstructionIdMemset: @@ -25942,6 +26215,7 @@ bool ir_has_side_effects(IrInstruction *instruction) { case IrInstructionIdTruncate: case IrInstructionIdIntType: case IrInstructionIdVectorType: + case IrInstructionIdShuffleVector: case IrInstructionIdBoolNot: case IrInstructionIdSliceSrc: case IrInstructionIdMemberCount: diff --git a/src/ir_print.cpp b/src/ir_print.cpp index f2877b46e6..8561ed4508 100644 --- a/src/ir_print.cpp +++ b/src/ir_print.cpp @@ -42,6 +42,8 @@ static const char* ir_instruction_type_str(IrInstruction* instruction) { switch (instruction->id) { case IrInstructionIdInvalid: return "Invalid"; + case IrInstructionIdShuffleVector: + return "Shuffle"; case IrInstructionIdDeclVarSrc: return "DeclVarSrc"; case IrInstructionIdDeclVarGen: @@ -1208,6 +1210,18 @@ static void ir_print_vector_type(IrPrint *irp, IrInstructionVectorType *instruct fprintf(irp->f, ")"); } +static void ir_print_shuffle_vector(IrPrint *irp, IrInstructionShuffleVector *instruction) { + fprintf(irp->f, "@shuffle("); + ir_print_other_instruction(irp, instruction->scalar_type); + fprintf(irp->f, ", "); + ir_print_other_instruction(irp, instruction->a); + fprintf(irp->f, ", "); + ir_print_other_instruction(irp, instruction->b); + fprintf(irp->f, ", "); + ir_print_other_instruction(irp, instruction->mask); + fprintf(irp->f, ")"); +} + static void ir_print_bool_not(IrPrint *irp, IrInstructionBoolNot *instruction) { fprintf(irp->f, "! "); ir_print_other_instruction(irp, instruction->value); @@ -2143,6 +2157,9 @@ static void ir_print_instruction(IrPrint *irp, IrInstruction *instruction, bool case IrInstructionIdVectorType: ir_print_vector_type(irp, (IrInstructionVectorType *)instruction); break; + case IrInstructionIdShuffleVector: + ir_print_shuffle_vector(irp, (IrInstructionShuffleVector *)instruction); + break; case IrInstructionIdBoolNot: ir_print_bool_not(irp, (IrInstructionBoolNot *)instruction); break; diff --git a/test/compile_errors.zig b/test/compile_errors.zig index 9d96d6f948..d9b4ee6a95 100644 --- a/test/compile_errors.zig +++ b/test/compile_errors.zig @@ -6484,6 +6484,19 @@ pub fn addCases(cases: *tests.CompileErrorContext) void { "tmp.zig:7:23: error: unable to evaluate constant expression", ); + cases.addTest( + "using LLVM syntax for @shuffle", + \\export fn entry() void { + \\ const v: @Vector(4, u32) = [4]u32{0, 1, 2, 3}; + \\ const x: @Vector(4, u32) = [4]u32{4, 5, 6, 7}; + \\ var z = @shuffle(u32, v, x, [8]i32{0, 1, 2, 3, 4, 5, 6, 7}); + \\} + , + "tmp.zig:4:39: error: mask index out of bounds", + "tmp.zig:4:39: note: when computing vector element at index 4", + "tmp.zig:4:39: note: selections from the second vector are specified with negative numbers", + ); + cases.addTest( "nested vectors", \\export fn entry() void { diff --git a/test/stage1/behavior/shuffle.zig b/test/stage1/behavior/shuffle.zig new file mode 100644 index 0000000000..70bff5991e --- /dev/null +++ b/test/stage1/behavior/shuffle.zig @@ -0,0 +1,57 @@ +const std = @import("std"); +const mem = std.mem; +const expect = std.testing.expect; + +test "@shuffle" { + const S = struct { + fn doTheTest() void { + var v: @Vector(4, i32) = [4]i32{ 2147483647, -2, 30, 40 }; + var x: @Vector(4, i32) = [4]i32{ 1, 2147483647, 3, 4 }; + const mask: @Vector(4, i32) = [4]i32{ 0, ~i32(2), 3, ~i32(3)}; + var res = @shuffle(i32, v, x, mask); + expect(mem.eql(i32, ([4]i32)(res), [4]i32{ 2147483647, 3, 40, 4 })); + + // Implicit cast from array (of mask) + res = @shuffle(i32, v, x, [4]i32{ 0, ~i32(2), 3, ~i32(3)}); + expect(mem.eql(i32, ([4]i32)(res), [4]i32{ 2147483647, 3, 40, 4 })); + + // Undefined + const mask2: @Vector(4, i32) = [4]i32{ 3, 1, 2, 0}; + res = @shuffle(i32, v, undefined, mask2); + expect(mem.eql(i32, ([4]i32)(res), [4]i32{ 40, -2, 30, 2147483647})); + + // Upcasting of b + var v2: @Vector(2, i32) = [2]i32{ 2147483647, undefined}; + const mask3: @Vector(4, i32) = [4]i32{ ~i32(0), 2, ~i32(0), 3}; + res = @shuffle(i32, x, v2, mask3); + expect(mem.eql(i32, ([4]i32)(res), [4]i32{ 2147483647, 3, 2147483647, 4 })); + + // Upcasting of a + var v3: @Vector(2, i32) = [2]i32{ 2147483647, -2}; + const mask4: @Vector(4, i32) = [4]i32{ 0, ~i32(2), 1, ~i32(3)}; + res = @shuffle(i32, v3, x, mask4); + expect(mem.eql(i32, ([4]i32)(res), [4]i32{ 2147483647, 3, -2, 4 })); + + // bool + { + var x2: @Vector(4, bool) = [4]bool{ false, true, false, true}; + var v4: @Vector(2, bool) = [2]bool{ true, false}; + const mask5: @Vector(4, i32) = [4]i32{ 0, ~i32(1), 1, 2}; + var res2 = @shuffle(bool, x2, v4, mask5); + expect(mem.eql(bool, ([4]bool)(res2), [4]bool{ false, false, true, false })); + } + + // FIXME re-enable when LLVM codegen is fixed + // https://bugs.llvm.org/show_bug.cgi?id=42803 + if (false) { + var x2: @Vector(3, bool) = [3]bool{ false, true, false}; + var v4: @Vector(2, bool) = [2]bool{ true, false}; + const mask5: @Vector(4, i32) = [4]i32{ 0, ~i32(1), 1, 2}; + var res2 = @shuffle(bool, x2, v4, mask5); + expect(mem.eql(bool, ([4]bool)(res2), [4]bool{ false, false, true, false })); + } + } + }; + S.doTheTest(); + comptime S.doTheTest(); +} -- cgit v1.2.3 From 76f53960778e84ab49730edb77b85490b07fbea2 Mon Sep 17 00:00:00 2001 From: Shawn Landden Date: Sun, 14 Jul 2019 09:22:37 -0500 Subject: @byteSwap on vectors --- src/all_types.hpp | 1 + src/codegen.cpp | 28 +++++++++++++----- src/ir.cpp | 62 ++++++++++++++++++++++++++++++++------- test/stage1/behavior/byteswap.zig | 11 +++++++ 4 files changed, 85 insertions(+), 17 deletions(-) (limited to 'src/all_types.hpp') diff --git a/src/all_types.hpp b/src/all_types.hpp index deb56cbb40..7887c06158 100644 --- a/src/all_types.hpp +++ b/src/all_types.hpp @@ -1771,6 +1771,7 @@ struct ZigLLVMFnKey { } overflow_arithmetic; struct { uint32_t bit_count; + uint32_t vector_len; // 0 means not a vector } bswap; struct { uint32_t bit_count; diff --git a/src/codegen.cpp b/src/codegen.cpp index 7676b3bbd0..6a575d32a2 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -4505,7 +4505,13 @@ static LLVMValueRef ir_render_optional_unwrap_ptr(CodeGen *g, IrExecutable *exec } } -static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *int_type, BuiltinFnId fn_id) { +static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *expr_type, BuiltinFnId fn_id) { + bool is_vector = expr_type->id == ZigTypeIdVector; + ZigType *int_type = is_vector ? expr_type->data.vector.elem_type : expr_type; + assert(int_type->id == ZigTypeIdInt); + uint32_t vector_len = 0; + if (is_vector) + vector_len = expr_type->data.vector.len; ZigLLVMFnKey key = {}; const char *fn_name; uint32_t n_args; @@ -4529,6 +4535,7 @@ static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *int_type, BuiltinFnI n_args = 1; key.id = ZigLLVMFnIdBswap; key.data.bswap.bit_count = (uint32_t)int_type->data.integral.bit_count; + key.data.bswap.vector_len = vector_len; } else if (fn_id == BuiltinFnIdBitReverse) { fn_name = "bitreverse"; n_args = 1; @@ -4543,12 +4550,15 @@ static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *int_type, BuiltinFnI return existing_entry->value; char llvm_name[64]; - sprintf(llvm_name, "llvm.%s.i%" PRIu32, fn_name, int_type->data.integral.bit_count); + if (is_vector) + sprintf(llvm_name, "llvm.%s.v%" PRIu32 "i%" PRIu32, fn_name, vector_len, int_type->data.integral.bit_count); + else + sprintf(llvm_name, "llvm.%s.i%" PRIu32, fn_name, int_type->data.integral.bit_count); LLVMTypeRef param_types[] = { - get_llvm_type(g, int_type), + get_llvm_type(g, expr_type), LLVMInt1Type(), }; - LLVMTypeRef fn_type = LLVMFunctionType(get_llvm_type(g, int_type), param_types, n_args, false); + LLVMTypeRef fn_type = LLVMFunctionType(get_llvm_type(g, expr_type), param_types, n_args, false); LLVMValueRef fn_val = LLVMAddFunction(g->module, llvm_name, fn_type); assert(LLVMGetIntrinsicID(fn_val)); @@ -5542,15 +5552,19 @@ static LLVMValueRef ir_render_mul_add(CodeGen *g, IrExecutable *executable, IrIn static LLVMValueRef ir_render_bswap(CodeGen *g, IrExecutable *executable, IrInstructionBswap *instruction) { LLVMValueRef op = ir_llvm_value(g, instruction->op); - ZigType *int_type = instruction->base.value.type; + ZigType *expr_type = instruction->base.value.type; + bool is_vector = expr_type->id == ZigTypeIdVector; + ZigType *int_type = is_vector ? expr_type->data.vector.elem_type : expr_type; assert(int_type->id == ZigTypeIdInt); if (int_type->data.integral.bit_count % 16 == 0) { - LLVMValueRef fn_val = get_int_builtin_fn(g, instruction->base.value.type, BuiltinFnIdBswap); + LLVMValueRef fn_val = get_int_builtin_fn(g, expr_type, BuiltinFnIdBswap); return LLVMBuildCall(g->builder, fn_val, &op, 1, ""); } // Not an even number of bytes, so we zext 1 byte, then bswap, shift right 1 byte, truncate ZigType *extended_type = get_int_type(g, int_type->data.integral.is_signed, int_type->data.integral.bit_count + 8); + if (is_vector) + extended_type = get_vector_type(g, expr_type->data.vector.len, extended_type); // aabbcc LLVMValueRef extended = LLVMBuildZExt(g->builder, op, get_llvm_type(g, extended_type), ""); // 00aabbcc @@ -5560,7 +5574,7 @@ static LLVMValueRef ir_render_bswap(CodeGen *g, IrExecutable *executable, IrInst LLVMValueRef shifted = ZigLLVMBuildLShrExact(g->builder, swapped, LLVMConstInt(get_llvm_type(g, extended_type), 8, false), ""); // 00ccbbaa - return LLVMBuildTrunc(g->builder, shifted, get_llvm_type(g, int_type), ""); + return LLVMBuildTrunc(g->builder, shifted, get_llvm_type(g, expr_type), ""); } static LLVMValueRef ir_render_bit_reverse(CodeGen *g, IrExecutable *executable, IrInstructionBitReverse *instruction) { diff --git a/src/ir.cpp b/src/ir.cpp index cbc00f0cfe..e8ef45a116 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -25253,16 +25253,42 @@ static IrInstruction *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstruct } static IrInstruction *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstructionBswap *instruction) { - ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child); - if (type_is_invalid(int_type)) + IrInstruction *op = instruction->op->child; + ZigType *type_expr = ir_resolve_type(ira, instruction->type->child); + if (type_is_invalid(type_expr)) return ira->codegen->invalid_instruction; - IrInstruction *op = ir_implicit_cast(ira, instruction->op->child, int_type); + if (type_expr->id != ZigTypeIdInt) { + ir_add_error(ira, instruction->type, + buf_sprintf("expected integer type, found '%s'", buf_ptr(&type_expr->name))); + if (type_expr->id == ZigTypeIdVector && + type_expr->data.vector.elem_type->id == ZigTypeIdInt) + ir_add_error(ira, instruction->type, + buf_sprintf("represent vectors with their scalar types, i.e. '%s'", + buf_ptr(&type_expr->data.vector.elem_type->name))); + return ira->codegen->invalid_instruction; + } + ZigType *int_type = type_expr; + + ZigType *expr_type = op->value.type; + bool is_vector = expr_type->id == ZigTypeIdVector; + ZigType *ret_type = int_type; + if (is_vector) + ret_type = get_vector_type(ira->codegen, expr_type->data.vector.len, int_type); + + op = ir_implicit_cast(ira, instruction->op->child, ret_type); if (type_is_invalid(op->value.type)) return ira->codegen->invalid_instruction; if (int_type->data.integral.bit_count == 0) { - IrInstruction *result = ir_const(ira, &instruction->base, int_type); + IrInstruction *result = ir_const(ira, &instruction->base, ret_type); + if (is_vector) { + expand_undef_array(ira->codegen, &result->value); + result->value.data.x_array.data.s_none.elements = + allocate(expr_type->data.vector.len); + for (unsigned i = 0; i < expr_type->data.vector.len; i++) + bigint_init_unsigned(&result->value.data.x_array.data.s_none.elements[i].data.x_bigint, 0); + } bigint_init_unsigned(&result->value.data.x_bigint, 0); return result; } @@ -25282,20 +25308,36 @@ static IrInstruction *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstruction if (val == nullptr) return ira->codegen->invalid_instruction; if (val->special == ConstValSpecialUndef) - return ir_const_undef(ira, &instruction->base, int_type); + return ir_const_undef(ira, &instruction->base, ret_type); - IrInstruction *result = ir_const(ira, &instruction->base, int_type); + IrInstruction *result = ir_const(ira, &instruction->base, ret_type); size_t buf_size = int_type->data.integral.bit_count / 8; uint8_t *buf = allocate_nonzero(buf_size); - bigint_write_twos_complement(&val->data.x_bigint, buf, int_type->data.integral.bit_count, true); - bigint_read_twos_complement(&result->value.data.x_bigint, buf, int_type->data.integral.bit_count, false, - int_type->data.integral.is_signed); + if (is_vector) { + expand_undef_array(ira->codegen, &result->value); + result->value.data.x_array.data.s_none.elements = + allocate(expr_type->data.vector.len); + for (unsigned i = 0; i < expr_type->data.vector.len; i++) { + ConstExprValue *cur = &val->data.x_array.data.s_none.elements[i]; + result->value.data.x_array.data.s_none.elements[i].special = cur->special; + if (cur->special == ConstValSpecialUndef) + continue; + bigint_write_twos_complement(&cur->data.x_bigint, buf, int_type->data.integral.bit_count, true); + bigint_read_twos_complement(&result->value.data.x_array.data.s_none.elements[i].data.x_bigint, + buf, int_type->data.integral.bit_count, false, + int_type->data.integral.is_signed); + } + } else { + bigint_write_twos_complement(&val->data.x_bigint, buf, int_type->data.integral.bit_count, true); + bigint_read_twos_complement(&result->value.data.x_bigint, buf, int_type->data.integral.bit_count, false, + int_type->data.integral.is_signed); + } return result; } IrInstruction *result = ir_build_bswap(&ira->new_irb, instruction->base.scope, instruction->base.source_node, nullptr, op); - result->value.type = int_type; + result->value.type = ret_type; return result; } diff --git a/test/stage1/behavior/byteswap.zig b/test/stage1/behavior/byteswap.zig index 3e7c34cb85..249db155b7 100644 --- a/test/stage1/behavior/byteswap.zig +++ b/test/stage1/behavior/byteswap.zig @@ -6,6 +6,11 @@ test "@byteSwap" { testByteSwap(); } +test "@byteSwap on vectors" { + comptime testVectorByteSwap(); + testVectorByteSwap(); +} + fn testByteSwap() void { expect(@byteSwap(u0, 0) == 0); expect(@byteSwap(u8, 0x12) == 0x12); @@ -30,3 +35,9 @@ fn testByteSwap() void { expect(@byteSwap(i128, @bitCast(i128, u128(0x123456789abcdef11121314151617181))) == @bitCast(i128, u128(0x8171615141312111f1debc9a78563412))); } + +fn testVectorByteSwap() void { + expect((@byteSwap(u8, @Vector(2, u8)([2]u8{0x12, 0x13})) == @Vector(2, u8)([2]u8{0x12, 0x13})).all); + expect((@byteSwap(u16, @Vector(2, u16)([2]u16{0x1234, 0x2345})) == @Vector(2, u16)([2]u16{0x3412, 0x4523})).all); + expect((@byteSwap(u24, @Vector(2, u24)([2]u24{0x123456, 0x234567})) == @Vector(2, u24)([2]u24{0x563412, 0x674523})).all); +} -- cgit v1.2.3 From 01577a3af480cff02c5f78864f8056487b3d3b44 Mon Sep 17 00:00:00 2001 From: Shawn Landden Date: Sun, 21 Jul 2019 10:41:43 -0500 Subject: `@splat` --- src/all_types.hpp | 9 +++++ src/codegen.cpp | 17 +++++++++ src/ir.cpp | 82 +++++++++++++++++++++++++++++++++++++++++ src/ir_print.cpp | 13 +++++++ test/compile_errors.zig | 10 +++++ test/stage1/behavior/vector.zig | 36 +++++++++++++----- 6 files changed, 157 insertions(+), 10 deletions(-) (limited to 'src/all_types.hpp') diff --git a/src/all_types.hpp b/src/all_types.hpp index 7887c06158..464a1d6ba4 100644 --- a/src/all_types.hpp +++ b/src/all_types.hpp @@ -1612,6 +1612,7 @@ enum BuiltinFnId { BuiltinFnIdIntType, BuiltinFnIdVectorType, BuiltinFnIdShuffle, + BuiltinFnIdSplat, BuiltinFnIdSetCold, BuiltinFnIdSetRuntimeSafety, BuiltinFnIdSetFloatMode, @@ -2431,6 +2432,7 @@ enum IrInstructionId { IrInstructionIdIntType, IrInstructionIdVectorType, IrInstructionIdShuffleVector, + IrInstructionIdSplat, IrInstructionIdBoolNot, IrInstructionIdMemset, IrInstructionIdMemcpy, @@ -3681,6 +3683,13 @@ struct IrInstructionShuffleVector { IrInstruction *mask; // This is in zig-format, not llvm format }; +struct IrInstructionSplat { + IrInstruction base; + + IrInstruction *len; + IrInstruction *scalar; +}; + struct IrInstructionAssertZero { IrInstruction base; diff --git a/src/codegen.cpp b/src/codegen.cpp index 54c02b288a..49681c20c1 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -4619,6 +4619,20 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, IrExecutable *executabl llvm_mask_value, ""); } +static LLVMValueRef ir_render_splat(CodeGen *g, IrExecutable *executable, IrInstructionSplat *instruction) { + uint64_t len = bigint_as_u64(&instruction->len->value.data.x_bigint); + LLVMValueRef wrapped_scalar_undef = LLVMGetUndef(instruction->base.value.type->llvm_type); + LLVMValueRef wrapped_scalar = LLVMBuildInsertElement(g->builder, wrapped_scalar_undef, + ir_llvm_value(g, instruction->scalar), + LLVMConstInt(LLVMInt32Type(), 0, false), + ""); + return LLVMBuildShuffleVector(g->builder, + wrapped_scalar, + wrapped_scalar_undef, + LLVMConstNull(LLVMVectorType(g->builtin_types.entry_u32->llvm_type, (uint32_t)len)), + ""); +} + static LLVMValueRef ir_render_pop_count(CodeGen *g, IrExecutable *executable, IrInstructionPopCount *instruction) { ZigType *int_type = instruction->op->value.type; LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdPopCount); @@ -6146,6 +6160,8 @@ static LLVMValueRef ir_render_instruction(CodeGen *g, IrExecutable *executable, return ir_render_spill_end(g, executable, (IrInstructionSpillEnd *)instruction); case IrInstructionIdShuffleVector: return ir_render_shuffle_vector(g, executable, (IrInstructionShuffleVector *) instruction); + case IrInstructionIdSplat: + return ir_render_splat(g, executable, (IrInstructionSplat *) instruction); } zig_unreachable(); } @@ -7837,6 +7853,7 @@ static void define_builtin_fns(CodeGen *g) { create_builtin_fn(g, BuiltinFnIdIntType, "IntType", 2); // TODO rename to Int create_builtin_fn(g, BuiltinFnIdVectorType, "Vector", 2); create_builtin_fn(g, BuiltinFnIdShuffle, "shuffle", 4); + create_builtin_fn(g, BuiltinFnIdSplat, "splat", 2); create_builtin_fn(g, BuiltinFnIdSetCold, "setCold", 1); create_builtin_fn(g, BuiltinFnIdSetRuntimeSafety, "setRuntimeSafety", 1); create_builtin_fn(g, BuiltinFnIdSetFloatMode, "setFloatMode", 1); diff --git a/src/ir.cpp b/src/ir.cpp index 1eba53ef45..8fca50c6f7 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -721,6 +721,10 @@ static constexpr IrInstructionId ir_instruction_id(IrInstructionShuffleVector *) return IrInstructionIdShuffleVector; } +static constexpr IrInstructionId ir_instruction_id(IrInstructionSplat *) { + return IrInstructionIdSplat; +} + static constexpr IrInstructionId ir_instruction_id(IrInstructionBoolNot *) { return IrInstructionIdBoolNot; } @@ -2300,6 +2304,19 @@ static IrInstruction *ir_build_shuffle_vector(IrBuilder *irb, Scope *scope, AstN return &instruction->base; } +static IrInstruction *ir_build_splat(IrBuilder *irb, Scope *scope, AstNode *source_node, + IrInstruction *len, IrInstruction *scalar) +{ + IrInstructionSplat *instruction = ir_build_instruction(irb, scope, source_node); + instruction->len = len; + instruction->scalar = scalar; + + ir_ref_instruction(len, irb->current_basic_block); + ir_ref_instruction(scalar, irb->current_basic_block); + + return &instruction->base; +} + static IrInstruction *ir_build_bool_not(IrBuilder *irb, Scope *scope, AstNode *source_node, IrInstruction *value) { IrInstructionBoolNot *instruction = ir_build_instruction(irb, scope, source_node); instruction->value = value; @@ -4985,6 +5002,22 @@ static IrInstruction *ir_gen_builtin_fn_call(IrBuilder *irb, Scope *scope, AstNo arg0_value, arg1_value, arg2_value, arg3_value); return ir_lval_wrap(irb, scope, shuffle_vector, lval, result_loc); } + case BuiltinFnIdSplat: + { + AstNode *arg0_node = node->data.fn_call_expr.params.at(0); + IrInstruction *arg0_value = ir_gen_node(irb, arg0_node, scope); + if (arg0_value == irb->codegen->invalid_instruction) + return arg0_value; + + AstNode *arg1_node = node->data.fn_call_expr.params.at(1); + IrInstruction *arg1_value = ir_gen_node(irb, arg1_node, scope); + if (arg1_value == irb->codegen->invalid_instruction) + return arg1_value; + + IrInstruction *splat = ir_build_splat(irb, scope, node, + arg0_value, arg1_value); + return ir_lval_wrap(irb, scope, splat, lval, result_loc); + } case BuiltinFnIdMemcpy: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); @@ -22324,6 +22357,52 @@ static IrInstruction *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, IrIn return ir_analyze_shuffle_vector(ira, &instruction->base, scalar_type, a, b, mask); } +static IrInstruction *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstructionSplat *instruction) { + IrInstruction *len = instruction->len->child; + if (type_is_invalid(len->value.type)) + return ira->codegen->invalid_instruction; + + IrInstruction *scalar = instruction->scalar->child; + if (type_is_invalid(scalar->value.type)) + return ira->codegen->invalid_instruction; + + uint64_t len_int; + if (!ir_resolve_unsigned(ira, len, ira->codegen->builtin_types.entry_u32, &len_int)) { + ir_add_error(ira, len, + buf_sprintf("splat length must be comptime")); + return ira->codegen->invalid_instruction; + } + + if (!is_valid_vector_elem_type(scalar->value.type)) { + ir_add_error(ira, len, + buf_sprintf("vector element type must be integer, float, bool, or pointer; '%s' is invalid", + buf_ptr(&scalar->value.type->name))); + return ira->codegen->invalid_instruction; + } + + ZigType *return_type = get_vector_type(ira->codegen, len_int, scalar->value.type); + + if (instr_is_comptime(scalar)) { + IrInstruction *result = ir_const_undef(ira, scalar, return_type); + result->value.data.x_array.data.s_none.elements = + allocate(len_int); + for (uint32_t i = 0; i < len_int; i++) { + result->value.data.x_array.data.s_none.elements[i] = + scalar->value; + } + result->value.type = return_type; + result->value.special = ConstValSpecialStatic; + return result; + } + + IrInstruction *result = ir_build_splat(&ira->new_irb, + instruction->base.scope, instruction->base.source_node, + instruction->len->child, instruction->scalar->child); + result->value.type = return_type; + result->value.special = ConstValSpecialRuntime; + return result; +} + static IrInstruction *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstructionBoolNot *instruction) { IrInstruction *value = instruction->value->child; if (type_is_invalid(value->value.type)) @@ -25908,6 +25987,8 @@ static IrInstruction *ir_analyze_instruction_base(IrAnalyze *ira, IrInstruction return ir_analyze_instruction_vector_type(ira, (IrInstructionVectorType *)instruction); case IrInstructionIdShuffleVector: return ir_analyze_instruction_shuffle_vector(ira, (IrInstructionShuffleVector *)instruction); + case IrInstructionIdSplat: + return ir_analyze_instruction_splat(ira, (IrInstructionSplat *)instruction); case IrInstructionIdBoolNot: return ir_analyze_instruction_bool_not(ira, (IrInstructionBoolNot *)instruction); case IrInstructionIdMemset: @@ -26244,6 +26325,7 @@ bool ir_has_side_effects(IrInstruction *instruction) { case IrInstructionIdIntType: case IrInstructionIdVectorType: case IrInstructionIdShuffleVector: + case IrInstructionIdSplat: case IrInstructionIdBoolNot: case IrInstructionIdSliceSrc: case IrInstructionIdMemberCount: diff --git a/src/ir_print.cpp b/src/ir_print.cpp index 8561ed4508..0dee7d342a 100644 --- a/src/ir_print.cpp +++ b/src/ir_print.cpp @@ -44,6 +44,8 @@ static const char* ir_instruction_type_str(IrInstruction* instruction) { return "Invalid"; case IrInstructionIdShuffleVector: return "Shuffle"; + case IrInstructionIdSplat: + return "Splat"; case IrInstructionIdDeclVarSrc: return "DeclVarSrc"; case IrInstructionIdDeclVarGen: @@ -1222,6 +1224,14 @@ static void ir_print_shuffle_vector(IrPrint *irp, IrInstructionShuffleVector *in fprintf(irp->f, ")"); } +static void ir_print_splat(IrPrint *irp, IrInstructionSplat *instruction) { + fprintf(irp->f, "@splat("); + ir_print_other_instruction(irp, instruction->len); + fprintf(irp->f, ", "); + ir_print_other_instruction(irp, instruction->scalar); + fprintf(irp->f, ")"); +} + static void ir_print_bool_not(IrPrint *irp, IrInstructionBoolNot *instruction) { fprintf(irp->f, "! "); ir_print_other_instruction(irp, instruction->value); @@ -2160,6 +2170,9 @@ static void ir_print_instruction(IrPrint *irp, IrInstruction *instruction, bool case IrInstructionIdShuffleVector: ir_print_shuffle_vector(irp, (IrInstructionShuffleVector *)instruction); break; + case IrInstructionIdSplat: + ir_print_splat(irp, (IrInstructionSplat *)instruction); + break; case IrInstructionIdBoolNot: ir_print_bool_not(irp, (IrInstructionBoolNot *)instruction); break; diff --git a/test/compile_errors.zig b/test/compile_errors.zig index 1fe3fc58ab..2909bffc3b 100644 --- a/test/compile_errors.zig +++ b/test/compile_errors.zig @@ -6507,6 +6507,16 @@ pub fn addCases(cases: *tests.CompileErrorContext) void { "tmp.zig:2:26: error: vector element type must be integer, float, bool, or pointer; '@Vector(4, u8)' is invalid", ); + cases.addTest( + "bad @splat type", + \\export fn entry() void { + \\ const c = 4; + \\ var v = @splat(4, c); + \\} + , + "tmp.zig:3:20: error: vector element type must be integer, float, bool, or pointer; 'comptime_int' is invalid", + ); + cases.add("compileLog of tagged enum doesn't crash the compiler", \\const Bar = union(enum(u32)) { \\ X: i32 = 1 diff --git a/test/stage1/behavior/vector.zig b/test/stage1/behavior/vector.zig index 27277b5e52..88a332d87b 100644 --- a/test/stage1/behavior/vector.zig +++ b/test/stage1/behavior/vector.zig @@ -35,12 +35,12 @@ test "vector bin compares with mem.eql" { fn doTheTest() void { var v: @Vector(4, i32) = [4]i32{ 2147483647, -2, 30, 40 }; var x: @Vector(4, i32) = [4]i32{ 1, 2147483647, 30, 4 }; - expect(mem.eql(bool, ([4]bool)(v == x), [4]bool{ false, false, true, false})); - expect(mem.eql(bool, ([4]bool)(v != x), [4]bool{ true, true, false, true})); - expect(mem.eql(bool, ([4]bool)(v < x), [4]bool{ false, true, false, false})); - expect(mem.eql(bool, ([4]bool)(v > x), [4]bool{ true, false, false, true})); - expect(mem.eql(bool, ([4]bool)(v <= x), [4]bool{ false, true, true, false})); - expect(mem.eql(bool, ([4]bool)(v >= x), [4]bool{ true, false, true, true})); + expect(mem.eql(bool, ([4]bool)(v == x), [4]bool{ false, false, true, false })); + expect(mem.eql(bool, ([4]bool)(v != x), [4]bool{ true, true, false, true })); + expect(mem.eql(bool, ([4]bool)(v < x), [4]bool{ false, true, false, false })); + expect(mem.eql(bool, ([4]bool)(v > x), [4]bool{ true, false, false, true })); + expect(mem.eql(bool, ([4]bool)(v <= x), [4]bool{ false, true, true, false })); + expect(mem.eql(bool, ([4]bool)(v >= x), [4]bool{ true, false, true, true })); } }; S.doTheTest(); @@ -114,22 +114,22 @@ test "vector casts of sizes not divisable by 8" { const S = struct { fn doTheTest() void { { - var v: @Vector(4, u3) = [4]u3{ 5, 2, 3, 0}; + var v: @Vector(4, u3) = [4]u3{ 5, 2, 3, 0 }; var x: [4]u3 = v; expect(mem.eql(u3, x, ([4]u3)(v))); } { - var v: @Vector(4, u2) = [4]u2{ 1, 2, 3, 0}; + var v: @Vector(4, u2) = [4]u2{ 1, 2, 3, 0 }; var x: [4]u2 = v; expect(mem.eql(u2, x, ([4]u2)(v))); } { - var v: @Vector(4, u1) = [4]u1{ 1, 0, 1, 0}; + var v: @Vector(4, u1) = [4]u1{ 1, 0, 1, 0 }; var x: [4]u1 = v; expect(mem.eql(u1, x, ([4]u1)(v))); } { - var v: @Vector(4, bool) = [4]bool{ false, false, true, false}; + var v: @Vector(4, bool) = [4]bool{ false, false, true, false }; var x: [4]bool = v; expect(mem.eql(bool, x, ([4]bool)(v))); } @@ -138,3 +138,19 @@ test "vector casts of sizes not divisable by 8" { S.doTheTest(); comptime S.doTheTest(); } + +test "vector @splat" { + const S = struct { + fn doTheTest() void { + var v: u32 = 5; + var x = @splat(4, v); + expect(@typeOf(x) == @Vector(4, u32)); + expect(x[0] == 5); + expect(x[1] == 5); + expect(x[2] == 5); + expect(x[3] == 5); + } + }; + S.doTheTest(); + comptime S.doTheTest(); +} -- cgit v1.2.3 From 005a54a853a77b9c28551490fc08dc37cd7d7715 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Thu, 19 Sep 2019 10:48:04 -0400 Subject: fixups for `@splat` * Fix codegen for splat - instead of giving vectors of length N to shufflevector for both of the operands, it gives vectors of length 1. The mask vector is the only one that needs N elements. * Separate Splat into SplatSrc and SplatGen; the `len` is not needed once it gets to codegen since it is redundant with the result type. * Refactor compile error for wrong vector element type so that the compile error message is not duplicated in zig source code * Improve implementation to correctly handle comptime values such as undefined and lazy values. * Improve compile error for bad vector element type to point to the correct place. * Delete dead code. * Modify behavior test to use an array cast instead of vector element indexing since I'm merging this splat commit out-of-order from Shawn's patch set. --- src/all_types.hpp | 11 ++++- src/codegen.cpp | 27 ++++++------ src/ir.cpp | 95 ++++++++++++++++++++++++----------------- src/ir_print.cpp | 21 ++++++--- test/compile_errors.zig | 2 +- test/stage1/behavior/vector.zig | 9 ++-- 6 files changed, 101 insertions(+), 64 deletions(-) (limited to 'src/all_types.hpp') diff --git a/src/all_types.hpp b/src/all_types.hpp index 464a1d6ba4..695f22ac90 100644 --- a/src/all_types.hpp +++ b/src/all_types.hpp @@ -2432,7 +2432,8 @@ enum IrInstructionId { IrInstructionIdIntType, IrInstructionIdVectorType, IrInstructionIdShuffleVector, - IrInstructionIdSplat, + IrInstructionIdSplatSrc, + IrInstructionIdSplatGen, IrInstructionIdBoolNot, IrInstructionIdMemset, IrInstructionIdMemcpy, @@ -3683,13 +3684,19 @@ struct IrInstructionShuffleVector { IrInstruction *mask; // This is in zig-format, not llvm format }; -struct IrInstructionSplat { +struct IrInstructionSplatSrc { IrInstruction base; IrInstruction *len; IrInstruction *scalar; }; +struct IrInstructionSplatGen { + IrInstruction base; + + IrInstruction *scalar; +}; + struct IrInstructionAssertZero { IrInstruction base; diff --git a/src/codegen.cpp b/src/codegen.cpp index 49681c20c1..b0817e8eb8 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -4619,18 +4619,16 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, IrExecutable *executabl llvm_mask_value, ""); } -static LLVMValueRef ir_render_splat(CodeGen *g, IrExecutable *executable, IrInstructionSplat *instruction) { - uint64_t len = bigint_as_u64(&instruction->len->value.data.x_bigint); - LLVMValueRef wrapped_scalar_undef = LLVMGetUndef(instruction->base.value.type->llvm_type); - LLVMValueRef wrapped_scalar = LLVMBuildInsertElement(g->builder, wrapped_scalar_undef, - ir_llvm_value(g, instruction->scalar), - LLVMConstInt(LLVMInt32Type(), 0, false), - ""); - return LLVMBuildShuffleVector(g->builder, - wrapped_scalar, - wrapped_scalar_undef, - LLVMConstNull(LLVMVectorType(g->builtin_types.entry_u32->llvm_type, (uint32_t)len)), - ""); +static LLVMValueRef ir_render_splat(CodeGen *g, IrExecutable *executable, IrInstructionSplatGen *instruction) { + ZigType *result_type = instruction->base.value.type; + src_assert(result_type->id == ZigTypeIdVector, instruction->base.source_node); + uint32_t len = result_type->data.vector.len; + LLVMTypeRef op_llvm_type = LLVMVectorType(get_llvm_type(g, instruction->scalar->value.type), 1); + LLVMTypeRef mask_llvm_type = LLVMVectorType(LLVMInt32Type(), len); + LLVMValueRef undef_vector = LLVMGetUndef(op_llvm_type); + LLVMValueRef op_vector = LLVMBuildInsertElement(g->builder, undef_vector, + ir_llvm_value(g, instruction->scalar), LLVMConstInt(LLVMInt32Type(), 0, false), ""); + return LLVMBuildShuffleVector(g->builder, op_vector, undef_vector, LLVMConstNull(mask_llvm_type), ""); } static LLVMValueRef ir_render_pop_count(CodeGen *g, IrExecutable *executable, IrInstructionPopCount *instruction) { @@ -6000,6 +5998,7 @@ static LLVMValueRef ir_render_instruction(CodeGen *g, IrExecutable *executable, case IrInstructionIdFrameSizeSrc: case IrInstructionIdAllocaGen: case IrInstructionIdAwaitSrc: + case IrInstructionIdSplatSrc: zig_unreachable(); case IrInstructionIdDeclVarGen: @@ -6160,8 +6159,8 @@ static LLVMValueRef ir_render_instruction(CodeGen *g, IrExecutable *executable, return ir_render_spill_end(g, executable, (IrInstructionSpillEnd *)instruction); case IrInstructionIdShuffleVector: return ir_render_shuffle_vector(g, executable, (IrInstructionShuffleVector *) instruction); - case IrInstructionIdSplat: - return ir_render_splat(g, executable, (IrInstructionSplat *) instruction); + case IrInstructionIdSplatGen: + return ir_render_splat(g, executable, (IrInstructionSplatGen *) instruction); } zig_unreachable(); } diff --git a/src/ir.cpp b/src/ir.cpp index 8fca50c6f7..0c48a2f982 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -721,8 +721,12 @@ static constexpr IrInstructionId ir_instruction_id(IrInstructionShuffleVector *) return IrInstructionIdShuffleVector; } -static constexpr IrInstructionId ir_instruction_id(IrInstructionSplat *) { - return IrInstructionIdSplat; +static constexpr IrInstructionId ir_instruction_id(IrInstructionSplatSrc *) { + return IrInstructionIdSplatSrc; +} + +static constexpr IrInstructionId ir_instruction_id(IrInstructionSplatGen *) { + return IrInstructionIdSplatGen; } static constexpr IrInstructionId ir_instruction_id(IrInstructionBoolNot *) { @@ -2304,10 +2308,10 @@ static IrInstruction *ir_build_shuffle_vector(IrBuilder *irb, Scope *scope, AstN return &instruction->base; } -static IrInstruction *ir_build_splat(IrBuilder *irb, Scope *scope, AstNode *source_node, +static IrInstruction *ir_build_splat_src(IrBuilder *irb, Scope *scope, AstNode *source_node, IrInstruction *len, IrInstruction *scalar) { - IrInstructionSplat *instruction = ir_build_instruction(irb, scope, source_node); + IrInstructionSplatSrc *instruction = ir_build_instruction(irb, scope, source_node); instruction->len = len; instruction->scalar = scalar; @@ -2373,6 +2377,19 @@ static IrInstruction *ir_build_slice_src(IrBuilder *irb, Scope *scope, AstNode * return &instruction->base; } +static IrInstruction *ir_build_splat_gen(IrAnalyze *ira, IrInstruction *source_instruction, ZigType *result_type, + IrInstruction *scalar) +{ + IrInstructionSplatGen *instruction = ir_build_instruction( + &ira->new_irb, source_instruction->scope, source_instruction->source_node); + instruction->base.value.type = result_type; + instruction->scalar = scalar; + + ir_ref_instruction(scalar, ira->new_irb.current_basic_block); + + return &instruction->base; +} + static IrInstruction *ir_build_slice_gen(IrAnalyze *ira, IrInstruction *source_instruction, ZigType *slice_type, IrInstruction *ptr, IrInstruction *start, IrInstruction *end, bool safety_check_on, IrInstruction *result_loc) { @@ -5014,7 +5031,7 @@ static IrInstruction *ir_gen_builtin_fn_call(IrBuilder *irb, Scope *scope, AstNo if (arg1_value == irb->codegen->invalid_instruction) return arg1_value; - IrInstruction *splat = ir_build_splat(irb, scope, node, + IrInstruction *splat = ir_build_splat_src(irb, scope, node, arg0_value, arg1_value); return ir_lval_wrap(irb, scope, splat, lval, result_loc); } @@ -11082,16 +11099,23 @@ static ZigType *ir_resolve_type(IrAnalyze *ira, IrInstruction *type_value) { return ir_resolve_const_type(ira->codegen, ira->new_irb.exec, type_value->source_node, val); } +static Error ir_validate_vector_elem_type(IrAnalyze *ira, IrInstruction *source_instr, ZigType *elem_type) { + if (!is_valid_vector_elem_type(elem_type)) { + ir_add_error(ira, source_instr, + buf_sprintf("vector element type must be integer, float, bool, or pointer; '%s' is invalid", + buf_ptr(&elem_type->name))); + return ErrorSemanticAnalyzeFail; + } + return ErrorNone; +} + static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstruction *elem_type_value) { + Error err; ZigType *elem_type = ir_resolve_type(ira, elem_type_value); if (type_is_invalid(elem_type)) return ira->codegen->builtin_types.entry_invalid; - if (!is_valid_vector_elem_type(elem_type)) { - ir_add_error(ira, elem_type_value, - buf_sprintf("vector element type must be integer, float, bool, or pointer; '%s' is invalid", - buf_ptr(&elem_type->name))); + if ((err = ir_validate_vector_elem_type(ira, elem_type_value, elem_type))) return ira->codegen->builtin_types.entry_invalid; - } return elem_type; } @@ -22357,7 +22381,9 @@ static IrInstruction *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, IrIn return ir_analyze_shuffle_vector(ira, &instruction->base, scalar_type, a, b, mask); } -static IrInstruction *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstructionSplat *instruction) { +static IrInstruction *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstructionSplatSrc *instruction) { + Error err; + IrInstruction *len = instruction->len->child; if (type_is_invalid(len->value.type)) return ira->codegen->invalid_instruction; @@ -22366,41 +22392,32 @@ static IrInstruction *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstruction if (type_is_invalid(scalar->value.type)) return ira->codegen->invalid_instruction; - uint64_t len_int; - if (!ir_resolve_unsigned(ira, len, ira->codegen->builtin_types.entry_u32, &len_int)) { - ir_add_error(ira, len, - buf_sprintf("splat length must be comptime")); + uint64_t len_u64; + if (!ir_resolve_unsigned(ira, len, ira->codegen->builtin_types.entry_u32, &len_u64)) return ira->codegen->invalid_instruction; - } + uint32_t len_int = len_u64; - if (!is_valid_vector_elem_type(scalar->value.type)) { - ir_add_error(ira, len, - buf_sprintf("vector element type must be integer, float, bool, or pointer; '%s' is invalid", - buf_ptr(&scalar->value.type->name))); + if ((err = ir_validate_vector_elem_type(ira, scalar, scalar->value.type))) return ira->codegen->invalid_instruction; - } ZigType *return_type = get_vector_type(ira->codegen, len_int, scalar->value.type); if (instr_is_comptime(scalar)) { - IrInstruction *result = ir_const_undef(ira, scalar, return_type); - result->value.data.x_array.data.s_none.elements = - allocate(len_int); - for (uint32_t i = 0; i < len_int; i++) { - result->value.data.x_array.data.s_none.elements[i] = - scalar->value; + ConstExprValue *scalar_val = ir_resolve_const(ira, scalar, UndefOk); + if (scalar_val == nullptr) + return ira->codegen->invalid_instruction; + if (scalar_val->special == ConstValSpecialUndef) + return ir_const_undef(ira, &instruction->base, return_type); + + IrInstruction *result = ir_const(ira, &instruction->base, return_type); + result->value.data.x_array.data.s_none.elements = create_const_vals(len_int); + for (uint32_t i = 0; i < len_int; i += 1) { + copy_const_val(&result->value.data.x_array.data.s_none.elements[i], scalar_val, false); } - result->value.type = return_type; - result->value.special = ConstValSpecialStatic; return result; } - IrInstruction *result = ir_build_splat(&ira->new_irb, - instruction->base.scope, instruction->base.source_node, - instruction->len->child, instruction->scalar->child); - result->value.type = return_type; - result->value.special = ConstValSpecialRuntime; - return result; + return ir_build_splat_gen(ira, &instruction->base, return_type, scalar); } static IrInstruction *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstructionBoolNot *instruction) { @@ -25857,6 +25874,7 @@ static IrInstruction *ir_analyze_instruction_base(IrAnalyze *ira, IrInstruction case IrInstructionIdTestErrGen: case IrInstructionIdFrameSizeGen: case IrInstructionIdAwaitGen: + case IrInstructionIdSplatGen: zig_unreachable(); case IrInstructionIdReturn: @@ -25987,8 +26005,8 @@ static IrInstruction *ir_analyze_instruction_base(IrAnalyze *ira, IrInstruction return ir_analyze_instruction_vector_type(ira, (IrInstructionVectorType *)instruction); case IrInstructionIdShuffleVector: return ir_analyze_instruction_shuffle_vector(ira, (IrInstructionShuffleVector *)instruction); - case IrInstructionIdSplat: - return ir_analyze_instruction_splat(ira, (IrInstructionSplat *)instruction); + case IrInstructionIdSplatSrc: + return ir_analyze_instruction_splat(ira, (IrInstructionSplatSrc *)instruction); case IrInstructionIdBoolNot: return ir_analyze_instruction_bool_not(ira, (IrInstructionBoolNot *)instruction); case IrInstructionIdMemset: @@ -26325,7 +26343,8 @@ bool ir_has_side_effects(IrInstruction *instruction) { case IrInstructionIdIntType: case IrInstructionIdVectorType: case IrInstructionIdShuffleVector: - case IrInstructionIdSplat: + case IrInstructionIdSplatSrc: + case IrInstructionIdSplatGen: case IrInstructionIdBoolNot: case IrInstructionIdSliceSrc: case IrInstructionIdMemberCount: diff --git a/src/ir_print.cpp b/src/ir_print.cpp index 0dee7d342a..aae65d50a9 100644 --- a/src/ir_print.cpp +++ b/src/ir_print.cpp @@ -44,8 +44,10 @@ static const char* ir_instruction_type_str(IrInstruction* instruction) { return "Invalid"; case IrInstructionIdShuffleVector: return "Shuffle"; - case IrInstructionIdSplat: - return "Splat"; + case IrInstructionIdSplatSrc: + return "SplatSrc"; + case IrInstructionIdSplatGen: + return "SplatGen"; case IrInstructionIdDeclVarSrc: return "DeclVarSrc"; case IrInstructionIdDeclVarGen: @@ -1224,7 +1226,7 @@ static void ir_print_shuffle_vector(IrPrint *irp, IrInstructionShuffleVector *in fprintf(irp->f, ")"); } -static void ir_print_splat(IrPrint *irp, IrInstructionSplat *instruction) { +static void ir_print_splat_src(IrPrint *irp, IrInstructionSplatSrc *instruction) { fprintf(irp->f, "@splat("); ir_print_other_instruction(irp, instruction->len); fprintf(irp->f, ", "); @@ -1232,6 +1234,12 @@ static void ir_print_splat(IrPrint *irp, IrInstructionSplat *instruction) { fprintf(irp->f, ")"); } +static void ir_print_splat_gen(IrPrint *irp, IrInstructionSplatGen *instruction) { + fprintf(irp->f, "@splat("); + ir_print_other_instruction(irp, instruction->scalar); + fprintf(irp->f, ")"); +} + static void ir_print_bool_not(IrPrint *irp, IrInstructionBoolNot *instruction) { fprintf(irp->f, "! "); ir_print_other_instruction(irp, instruction->value); @@ -2170,8 +2178,11 @@ static void ir_print_instruction(IrPrint *irp, IrInstruction *instruction, bool case IrInstructionIdShuffleVector: ir_print_shuffle_vector(irp, (IrInstructionShuffleVector *)instruction); break; - case IrInstructionIdSplat: - ir_print_splat(irp, (IrInstructionSplat *)instruction); + case IrInstructionIdSplatSrc: + ir_print_splat_src(irp, (IrInstructionSplatSrc *)instruction); + break; + case IrInstructionIdSplatGen: + ir_print_splat_gen(irp, (IrInstructionSplatGen *)instruction); break; case IrInstructionIdBoolNot: ir_print_bool_not(irp, (IrInstructionBoolNot *)instruction); diff --git a/test/compile_errors.zig b/test/compile_errors.zig index 2909bffc3b..034800fd4c 100644 --- a/test/compile_errors.zig +++ b/test/compile_errors.zig @@ -6514,7 +6514,7 @@ pub fn addCases(cases: *tests.CompileErrorContext) void { \\ var v = @splat(4, c); \\} , - "tmp.zig:3:20: error: vector element type must be integer, float, bool, or pointer; 'comptime_int' is invalid", + "tmp.zig:3:23: error: vector element type must be integer, float, bool, or pointer; 'comptime_int' is invalid", ); cases.add("compileLog of tagged enum doesn't crash the compiler", diff --git a/test/stage1/behavior/vector.zig b/test/stage1/behavior/vector.zig index 88a332d87b..d3a771fca8 100644 --- a/test/stage1/behavior/vector.zig +++ b/test/stage1/behavior/vector.zig @@ -145,10 +145,11 @@ test "vector @splat" { var v: u32 = 5; var x = @splat(4, v); expect(@typeOf(x) == @Vector(4, u32)); - expect(x[0] == 5); - expect(x[1] == 5); - expect(x[2] == 5); - expect(x[3] == 5); + var array_x: [4]u32 = x; + expect(array_x[0] == 5); + expect(array_x[1] == 5); + expect(array_x[2] == 5); + expect(array_x[3] == 5); } }; S.doTheTest(); -- cgit v1.2.3