From d6f997259487fc01b1aa6d24bdc7b960c4aaec46 Mon Sep 17 00:00:00 2001 From: Alex Rønne Petersen Date: Tue, 6 Aug 2024 22:34:20 +0200 Subject: all: Handle spirv in addition to spirv(32,64) where applicable. Some of this is arbitrary since spirv (as opposed to spirv32/spirv64) refers to the version with logical memory layout, i.e. no 'real' pointers. This change at least matches what clang does. --- src/Sema.zig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/Sema.zig') diff --git a/src/Sema.zig b/src/Sema.zig index 20daa78e9a..4fcb9c98c8 100644 --- a/src/Sema.zig +++ b/src/Sema.zig @@ -10038,11 +10038,11 @@ fn finishFunc( else => "x86_64", }, .Kernel => switch (arch) { - .nvptx, .nvptx64, .amdgcn, .spirv32, .spirv64 => null, + .nvptx, .nvptx64, .amdgcn, .spirv, .spirv32, .spirv64 => null, else => "nvptx, amdgcn and SPIR-V", }, .Fragment, .Vertex => switch (arch) { - .spirv32, .spirv64 => null, + .spirv, .spirv32, .spirv64 => null, else => "SPIR-V", }, })) |allowed_platform| { @@ -26703,7 +26703,7 @@ fn zirWorkItem( switch (target.cpu.arch) { // TODO: Allow for other GPU targets. - .amdgcn, .spirv64, .spirv32 => {}, + .amdgcn, .spirv, .spirv64, .spirv32 => {}, else => { return sema.fail(block, builtin_src, "builtin only available on GPU targets; targeted architecture is {s}", .{@tagName(target.cpu.arch)}); }, @@ -37323,9 +37323,9 @@ pub fn analyzeAsAddressSpace( const target = pt.zcu.getTarget(); const arch = target.cpu.arch; - const is_nv = arch == .nvptx or arch == .nvptx64; + const is_nv = arch.isNvptx(); const is_amd = arch == .amdgcn; - const is_spirv = arch == .spirv32 or arch == .spirv64; + const is_spirv = arch.isSpirV(); const is_gpu = is_nv or is_amd or is_spirv; const supported = switch (address_space) { -- cgit v1.2.3