From 3014a0d5f1dcbcfdcec3852ffd54f3c589fe3e83 Mon Sep 17 00:00:00 2001
From: Veikka Tuominen <git@vexu.eu>
Date: Thu, 30 Jun 2022 16:39:54 +0300
Subject: Sema: validate callconv

---
 src/Sema.zig | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

(limited to 'src/Sema.zig')

diff --git a/src/Sema.zig b/src/Sema.zig
index 08372bf7b3..0d568f8b38 100644
--- a/src/Sema.zig
+++ b/src/Sema.zig
@@ -7007,6 +7007,7 @@ fn funcCommon(
     noalias_bits: u32,
 ) CompileError!Air.Inst.Ref {
     const ret_ty_src: LazySrcLoc = .{ .node_offset_fn_type_ret_ty = src_node_offset };
+    const cc_src: LazySrcLoc = .{ .node_offset_fn_type_cc = src_node_offset };
 
     var is_generic = bare_return_type.tag() == .generic_poison or
         alignment == null or
@@ -7109,6 +7110,45 @@ fn funcCommon(
         const cc_workaround = cc orelse .Unspecified;
         const align_workaround = alignment orelse 0;
 
+        const arch = sema.mod.getTarget().cpu.arch;
+        if (switch (cc_workaround) {
+            .Unspecified, .C, .Naked, .Async, .Inline => null,
+            .Interrupt => switch (arch) {
+                .i386, .x86_64, .avr, .msp430 => null,
+                else => @as([]const u8, "i386, x86_64, AVR, and MSP430"),
+            },
+            .Signal => switch (arch) {
+                .avr => null,
+                else => @as([]const u8, "AVR"),
+            },
+            .Stdcall, .Fastcall, .Thiscall => switch (arch) {
+                .i386 => null,
+                else => @as([]const u8, "i386"),
+            },
+            .Vectorcall => switch (arch) {
+                .i386, .aarch64, .aarch64_be, .aarch64_32 => null,
+                else => @as([]const u8, "i386 and AArch64"),
+            },
+            .APCS, .AAPCS, .AAPCSVFP => switch (arch) {
+                .arm, .armeb, .aarch64, .aarch64_be, .aarch64_32 => null,
+                else => @as([]const u8, "ARM"),
+            },
+            .SysV, .Win64 => switch (arch) {
+                .x86_64 => null,
+                else => @as([]const u8, "x86_64"),
+            },
+            .PtxKernel => switch (arch) {
+                .nvptx, .nvptx64 => null,
+                else => @as([]const u8, "nvptx and nvptx64"),
+            },
+        }) |allowed_platform| {
+            return sema.fail(block, cc_src, "callconv '{s}' is only available on {s}, not {s}", .{
+                @tagName(cc_workaround),
+                allowed_platform,
+                @tagName(arch),
+            });
+        }
+
         break :fn_ty try Type.Tag.function.create(sema.arena, .{
             .param_types = param_types,
             .comptime_params = comptime_params.ptr,
-- 
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