From 0f5eda973e0c17b3f792cdb06674bf8d2863c8fb Mon Sep 17 00:00:00 2001
From: Andrew Kelley <andrew@ziglang.org>
Date: Sun, 31 Jan 2021 20:58:11 -0700
Subject: stage2: delete astgen for switch expressions

The astgen for switch expressions did not respect the ZIR rules of only
referencing instructions that are in scope:

  %14 = block_comptime_flat({
    %15 = block_comptime_flat({
      %16 = const(TypedValue{ .ty = comptime_int, .val = 1})
    })
    %17 = block_comptime_flat({
      %18 = const(TypedValue{ .ty = comptime_int, .val = 2})
    })
  })
  %19 = block({
    %20 = ref(%5)
    %21 = deref(%20)
    %22 = switchbr(%20, [%15, %17], {
      %15 => {
        %23 = const(TypedValue{ .ty = comptime_int, .val = 1})
        %24 = store(%10, %23)
        %25 = const(TypedValue{ .ty = void, .val = {}})
        %26 = break("label_19", %25)
      },
      %17 => {
        %27 = const(TypedValue{ .ty = comptime_int, .val = 2})
        %28 = store(%10, %27)
        %29 = const(TypedValue{ .ty = void, .val = {}})
        %30 = break("label_19", %29)
      }
    }, {
      %31 = unreachable_safe()
    }, special_prong=else)
  })

In this snippet you can see that the comptime expr referenced %15 and
%17 which are not in scope. There also was no test coverage for runtime
switch expressions.

Switch expressions will have to be re-introduced to follow these rules
and with some test coverage. There is some usable code being deleted in
this commit; it will be useful to reference when re-implementing switch
later.

A few more improvements to do while we're at it:
 * only use .ref result loc on switch target if any prongs obtain the
   payload with |*syntax|
   - this improvement should be done to if, while, and for as well.
   - this will remove the needless ref/deref instructions above
 * remove switchbr and add switch_block, which is both a block and a
   switch branch.
   - similarly we should remove loop and add loop_block.

This commit introduces a "force_comptime" flag into the GenZIR
scope. The main purpose of this will be to choose the "comptime"
variants of certain key zir instructions, such as function calls and
branches. We will be moving away from using the block_comptime_flat
ZIR instruction, and eventually deleting it.

This commit also contains miscellaneous fixes to this branch that bring
it to the state of passing all the tests.
---
 src/Module.zig | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

(limited to 'src/Module.zig')

diff --git a/src/Module.zig b/src/Module.zig
index 0bafc72e6b..b495afb336 100644
--- a/src/Module.zig
+++ b/src/Module.zig
@@ -375,6 +375,10 @@ pub const Scope = struct {
         }
     }
 
+    pub fn isComptime(self: *Scope) bool {
+        return self.getGenZIR().force_comptime;
+    }
+
     pub fn ownerDecl(self: *Scope) ?*Decl {
         return switch (self.tag) {
             .block => self.cast(Block).?.owner_decl,
@@ -712,6 +716,7 @@ pub const Scope = struct {
         parent: *Scope,
         decl: *Decl,
         arena: *Allocator,
+        force_comptime: bool,
         /// The first N instructions in a function body ZIR are arg instructions.
         instructions: std.ArrayListUnmanaged(*zir.Inst) = .{},
         label: ?Label = null,
@@ -1008,6 +1013,7 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool {
                 .decl = decl,
                 .arena = &fn_type_scope_arena.allocator,
                 .parent = &decl.container.base,
+                .force_comptime = true,
             };
             defer fn_type_scope.instructions.deinit(self.gpa);
 
@@ -1171,6 +1177,7 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool {
                     .decl = decl,
                     .arena = &decl_arena.allocator,
                     .parent = &decl.container.base,
+                    .force_comptime = false,
                 };
                 defer gen_scope.instructions.deinit(self.gpa);
 
@@ -1369,6 +1376,7 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool {
                     .decl = decl,
                     .arena = &gen_scope_arena.allocator,
                     .parent = &decl.container.base,
+                    .force_comptime = false,
                 };
                 defer gen_scope.instructions.deinit(self.gpa);
 
@@ -1428,6 +1436,7 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool {
                     .decl = decl,
                     .arena = &type_scope_arena.allocator,
                     .parent = &decl.container.base,
+                    .force_comptime = true,
                 };
                 defer type_scope.instructions.deinit(self.gpa);
 
@@ -1497,13 +1506,15 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool {
 
             decl.analysis = .in_progress;
 
-            // A comptime decl does not store any value so we can just deinit this arena after analysis is done.
+            // A comptime decl does not store any value so we can just deinit
+            // this arena after analysis is done.
             var analysis_arena = std.heap.ArenaAllocator.init(self.gpa);
             defer analysis_arena.deinit();
             var gen_scope: Scope.GenZIR = .{
                 .decl = decl,
                 .arena = &analysis_arena.allocator,
                 .parent = &decl.container.base,
+                .force_comptime = true,
             };
             defer gen_scope.instructions.deinit(self.gpa);
 
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