From 7adf15682ca263c7d4e0e5306517f22272310294 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Sun, 15 Aug 2021 23:09:55 -0700 Subject: update target CPU features with LLVM 13 rc1 data --- lib/std/target.zig | 1 + lib/std/target/aarch64.zig | 126 ++++++++++++++++++---- lib/std/target/amdgpu.zig | 263 +++++++++++++++++++++++++++++++++++++++++++-- lib/std/target/arc.zig | 39 +++++++ lib/std/target/arm.zig | 20 ++-- lib/std/target/hexagon.zig | 35 ++++++ lib/std/target/nvptx.zig | 26 +++++ lib/std/target/powerpc.zig | 35 +++++- lib/std/target/riscv.zig | 2 +- lib/std/target/systemz.zig | 76 +++++++++++++ lib/std/target/wasm.zig | 8 -- lib/std/target/x86.zig | 167 ++++++++++++++++++++++------ 12 files changed, 720 insertions(+), 78 deletions(-) create mode 100644 lib/std/target/arc.zig (limited to 'lib/std') diff --git a/lib/std/target.zig b/lib/std/target.zig index 1b9f0084c8..69800c9f8b 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -430,6 +430,7 @@ pub const Target = struct { }; pub const aarch64 = @import("target/aarch64.zig"); + pub const arc = @import("target/arc.zig"); pub const amdgpu = @import("target/amdgpu.zig"); pub const arm = @import("target/arm.zig"); pub const avr = @import("target/avr.zig"); diff --git a/lib/std/target/aarch64.zig b/lib/std/target/aarch64.zig index 1073cf1cdb..53363ee982 100644 --- a/lib/std/target/aarch64.zig +++ b/lib/std/target/aarch64.zig @@ -65,6 +65,7 @@ pub const Feature = enum { fuse_csel, fuse_literals, harden_sls_blr, + harden_sls_nocomdat, harden_sls_retbr, hcx, i8mm, @@ -81,6 +82,7 @@ pub const Feature = enum { neoverse_n2, neoverse_v1, no_neg_immediates, + no_zcz_fp, nv, outline_atomics, pan, @@ -120,6 +122,7 @@ pub const Feature = enum { reserve_x6, reserve_x7, reserve_x9, + rme, sb, sel2, sha2, @@ -128,6 +131,9 @@ pub const Feature = enum { slow_paired_128, slow_strqro_store, sm4, + sme, + sme_f64, + sme_i64, spe, spe_eef, specrestrict, @@ -148,7 +154,6 @@ pub const Feature = enum { tracev8_4, trbe, uaops, - use_aa, use_experimental_zeroing_pseudos, use_postra_scheduler, use_reciprocal_square_root, @@ -166,7 +171,6 @@ pub const Feature = enum { xs, zcm, zcz, - zcz_fp, zcz_fp_workaround, zcz_gp, }; @@ -594,6 +598,11 @@ pub const all_features = blk: { .description = "Harden against straight line speculation across BLR instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.harden_sls_nocomdat)] = .{ + .llvm_name = "harden-sls-nocomdat", + .description = "Generate thunk code for SLS mitigation in the normal text section", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.harden_sls_retbr)] = .{ .llvm_name = "harden-sls-retbr", .description = "Harden against straight line speculation across RET and BR instructions", @@ -660,8 +669,10 @@ pub const all_features = blk: { .crypto, .dotprod, .fullfp16, + .fuse_aes, .rcpc, .ssbs, + .use_postra_scheduler, .v8_2a, }), }; @@ -672,9 +683,11 @@ pub const all_features = blk: { .crypto, .dotprod, .fullfp16, + .fuse_aes, .rcpc, .spe, .ssbs, + .use_postra_scheduler, .v8_2a, }), }; @@ -683,10 +696,13 @@ pub const all_features = blk: { .description = "Neoverse N2 ARM processors", .dependencies = featureSet(&[_]Feature{ .bf16, + .crypto, .ete, + .fuse_aes, .i8mm, .mte, .sve2_bitperm, + .use_postra_scheduler, .v8_5a, }), }; @@ -714,6 +730,11 @@ pub const all_features = blk: { .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.no_zcz_fp)] = .{ + .llvm_name = "no-zcz-fp", + .description = "Has no zero-cycle zeroing instructions for FP registers", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.nv)] = .{ .llvm_name = "nv", .description = "Enable v8.4-A Nested Virtualization Enchancement", @@ -913,6 +934,11 @@ pub const all_features = blk: { .description = "Reserve X9, making it unavailable as a GPR", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.rme)] = .{ + .llvm_name = "rme", + .description = "Enable Realm Management Extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.sb)] = .{ .llvm_name = "sb", .description = "Enable v8.5 Speculation Barrier", @@ -959,6 +985,28 @@ pub const all_features = blk: { .neon, }), }; + result[@enumToInt(Feature.sme)] = .{ + .llvm_name = "sme", + .description = "Enable Scalable Matrix Extension (SME)", + .dependencies = featureSet(&[_]Feature{ + .bf16, + .sve2, + }), + }; + result[@enumToInt(Feature.sme_f64)] = .{ + .llvm_name = "sme-f64", + .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions", + .dependencies = featureSet(&[_]Feature{ + .sme, + }), + }; + result[@enumToInt(Feature.sme_i64)] = .{ + .llvm_name = "sme-i64", + .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions", + .dependencies = featureSet(&[_]Feature{ + .sme, + }), + }; result[@enumToInt(Feature.spe)] = .{ .llvm_name = "spe", .description = "Enable Statistical Profiling extension", @@ -1074,11 +1122,6 @@ pub const all_features = blk: { .description = "Enable v8.2 UAO PState", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.use_aa)] = .{ - .llvm_name = "use-aa", - .description = "Use alias analysis during codegen", - .dependencies = featureSet(&[_]Feature{}), - }; result[@enumToInt(Feature.use_experimental_zeroing_pseudos)] = .{ .llvm_name = "use-experimental-zeroing-pseudos", .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations", @@ -1251,15 +1294,9 @@ pub const all_features = blk: { .llvm_name = "zcz", .description = "Has zero-cycle zeroing instructions", .dependencies = featureSet(&[_]Feature{ - .zcz_fp, .zcz_gp, }), }; - result[@enumToInt(Feature.zcz_fp)] = .{ - .llvm_name = "zcz-fp", - .description = "Has zero-cycle zeroing instructions for FP registers", - .dependencies = featureSet(&[_]Feature{}), - }; result[@enumToInt(Feature.zcz_fp_workaround)] = .{ .llvm_name = "zcz-fp-workaround", .description = "The zero-cycle floating-point zeroing instruction has a bug", @@ -1403,7 +1440,62 @@ pub const cpu = struct { .name = "apple_latest", .llvm_name = "apple-latest", .features = featureSet(&[_]Feature{ - .apple_a13, + .aggressive_fma, + .alternate_sextload_cvt_f32_pattern, + .altnzcv, + .arith_bcc_fusion, + .arith_cbz_fusion, + .ccdp, + .crypto, + .disable_latency_sched_heuristic, + .fp16fml, + .fptoint, + .fuse_address, + .fuse_aes, + .fuse_arith_logic, + .fuse_crypto_eor, + .fuse_csel, + .fuse_literals, + .perfmon, + .predres, + .sb, + .sha3, + .specrestrict, + .ssbs, + .v8_4a, + .zcm, + .zcz, + }), + }; + pub const apple_m1 = CpuModel{ + .name = "apple_m1", + .llvm_name = "apple-m1", + .features = featureSet(&[_]Feature{ + .aggressive_fma, + .alternate_sextload_cvt_f32_pattern, + .altnzcv, + .arith_bcc_fusion, + .arith_cbz_fusion, + .ccdp, + .crypto, + .disable_latency_sched_heuristic, + .fp16fml, + .fptoint, + .fuse_address, + .fuse_aes, + .fuse_arith_logic, + .fuse_crypto_eor, + .fuse_csel, + .fuse_literals, + .perfmon, + .predres, + .sb, + .sha3, + .specrestrict, + .ssbs, + .v8_4a, + .zcm, + .zcz, }), }; pub const apple_s4 = CpuModel{ @@ -1459,7 +1551,6 @@ pub const cpu = struct { .custom_cheap_as_move, .fuse_aes, .perfmon, - .use_aa, .use_postra_scheduler, .v8a, }), @@ -1474,6 +1565,7 @@ pub const cpu = struct { .fuse_aes, .perfmon, .rcpc, + .use_postra_scheduler, .v8_2a, }), }; @@ -1649,7 +1741,6 @@ pub const cpu = struct { .use_postra_scheduler, .use_reciprocal_square_root, .v8a, - .zcz_fp, }), }; pub const exynos_m2 = CpuModel{ @@ -1666,7 +1757,6 @@ pub const cpu = struct { .slow_paired_128, .use_postra_scheduler, .v8a, - .zcz_fp, }), }; pub const exynos_m3 = CpuModel{ @@ -1686,7 +1776,6 @@ pub const cpu = struct { .predictable_select_expensive, .use_postra_scheduler, .v8a, - .zcz_fp, }), }; pub const exynos_m4 = CpuModel{ @@ -1824,7 +1913,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .strict_align, - .use_aa, .use_postra_scheduler, .v8_3a, }), diff --git a/lib/std/target/amdgpu.zig b/lib/std/target/amdgpu.zig index f8002071be..2fb8a6fa80 100644 --- a/lib/std/target/amdgpu.zig +++ b/lib/std/target/amdgpu.zig @@ -9,6 +9,7 @@ pub const Feature = enum { a16, add_no_carry_insts, aperture_regs, + architected_flat_scratch, atomic_fadd_insts, auto_waitcnt_before_barrier, ci_insts, @@ -20,11 +21,14 @@ pub const Feature = enum { dot4_insts, dot5_insts, dot6_insts, + dot7_insts, dpp, dpp8, + dpp_64bit, ds_src2_insts, enable_ds128, enable_prt_strict_null, + extended_image_insts, fast_denormal_f32, fast_fmaf, flat_address_space, @@ -36,16 +40,19 @@ pub const Feature = enum { fma_mix_insts, fmaf, fp64, + full_rate_64_ops, g16, gcn3_encoding, get_wave_id_inst, gfx10, gfx10_3_insts, + gfx10_a_encoding, gfx10_b_encoding, gfx10_insts, gfx7_gfx8_gfx9_insts, gfx8_insts, gfx9, + gfx90a_insts, gfx9_insts, half_rate_64_ops, image_gather4_d16_bug, @@ -70,11 +77,18 @@ pub const Feature = enum { mfma_inline_literal_bug, mimg_r128, movrel, + negative_scratch_offset_bug, + negative_unaligned_scratch_offset_bug, no_data_dep_hazard, no_sdst_cmpx, + nsa_clause_bug, nsa_encoding, + nsa_max_size_13, + nsa_max_size_5, nsa_to_vmem_bug, offset_3f_bug, + packed_fp32_ops, + packed_tid, pk_fmac_f16_inst, promote_alloca, r128_a16, @@ -92,11 +106,13 @@ pub const Feature = enum { sdwa_sdst, sea_islands, sgpr_init_bug, + shader_cycles_register, si_scheduler, smem_to_vector_write_hazard, southern_islands, sramecc, sramecc_support, + tgsplit, trap_handler, trig_reduced_range, unaligned_access_mode, @@ -149,6 +165,11 @@ pub const all_features = blk: { .description = "Has Memory Aperture Base and Size Registers", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.architected_flat_scratch)] = .{ + .llvm_name = "architected-flat-scratch", + .description = "Flat Scratch register is a readonly SPI initialized architected register", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.atomic_fadd_insts)] = .{ .llvm_name = "atomic-fadd-insts", .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions", @@ -183,7 +204,7 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.dot2_insts)] = .{ .llvm_name = "dot2-insts", - .description = "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", + .description = "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.dot3_insts)] = .{ @@ -206,6 +227,11 @@ pub const all_features = blk: { .description = "Has v_dot4c_i32_i8 instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.dot7_insts)] = .{ + .llvm_name = "dot7-insts", + .description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.dpp)] = .{ .llvm_name = "dpp", .description = "Support DPP (Data Parallel Primitives) extension", @@ -216,6 +242,11 @@ pub const all_features = blk: { .description = "Support DPP8 (Data Parallel Primitives) extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.dpp_64bit)] = .{ + .llvm_name = "dpp-64bit", + .description = "Support DPP (Data Parallel Primitives) extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.ds_src2_insts)] = .{ .llvm_name = "ds-src2-insts", .description = "Has ds_*_src2 instructions", @@ -231,6 +262,11 @@ pub const all_features = blk: { .description = "Enable zeroing of result registers for sparse texture fetches", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.extended_image_insts)] = .{ + .llvm_name = "extended-image-insts", + .description = "Support mips != 0, lod != 0, gather4, and get_lod", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.fast_denormal_f32)] = .{ .llvm_name = "fast-denormal-f32", .description = "Enabling denormals does not cause f32 instructions to run at f64 rates", @@ -268,7 +304,7 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.flat_segment_offset_bug)] = .{ .llvm_name = "flat-segment-offset-bug", - .description = "GFX10 bug, inst_offset ignored in flat segment", + .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.fma_mix_insts)] = .{ @@ -286,6 +322,11 @@ pub const all_features = blk: { .description = "Enable double precision operations", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.full_rate_64_ops)] = .{ + .llvm_name = "full-rate-64-ops", + .description = "Most fp64 instructions are full rate", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.g16)] = .{ .llvm_name = "g16", .description = "Support G16 for 16-bit gradient image operands", @@ -312,6 +353,7 @@ pub const all_features = blk: { .ci_insts, .dpp, .dpp8, + .extended_image_insts, .fast_denormal_f32, .fast_fmaf, .flat_address_space, @@ -334,6 +376,7 @@ pub const all_features = blk: { .pk_fmac_f16_inst, .register_banking, .s_memrealtime, + .s_memtime_inst, .sdwa, .sdwa_omod, .sdwa_scalar, @@ -350,6 +393,11 @@ pub const all_features = blk: { .description = "Additional instructions for GFX10.3", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.gfx10_a_encoding)] = .{ + .llvm_name = "gfx10_a-encoding", + .description = "Has BVH ray tracing instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.gfx10_b_encoding)] = .{ .llvm_name = "gfx10_b-encoding", .description = "Encoding format GFX10_B", @@ -379,7 +427,6 @@ pub const all_features = blk: { .aperture_regs, .ci_insts, .dpp, - .ds_src2_insts, .fast_denormal_f32, .fast_fmaf, .flat_address_space, @@ -394,7 +441,7 @@ pub const all_features = blk: { .int_clamp_insts, .inv_2pi_inline_imm, .localmemorysize65536, - .mad_mac_f32_insts, + .negative_scratch_offset_bug, .r128_a16, .s_memrealtime, .s_memtime_inst, @@ -413,6 +460,11 @@ pub const all_features = blk: { .xnack_support, }), }; + result[@enumToInt(Feature.gfx90a_insts)] = .{ + .llvm_name = "gfx90a-insts", + .description = "Additional instructions for GFX90A+", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.gfx9_insts)] = .{ .llvm_name = "gfx9-insts", .description = "Additional instructions for GFX9+", @@ -533,6 +585,16 @@ pub const all_features = blk: { .description = "Has v_movrel*_b32 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.negative_scratch_offset_bug)] = .{ + .llvm_name = "negative-scratch-offset-bug", + .description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.negative_unaligned_scratch_offset_bug)] = .{ + .llvm_name = "negative-unaligned-scratch-offset-bug", + .description = "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.no_data_dep_hazard)] = .{ .llvm_name = "no-data-dep-hazard", .description = "Does not need SW waitstates", @@ -543,11 +605,26 @@ pub const all_features = blk: { .description = "V_CMPX does not write VCC/SGPR in addition to EXEC", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.nsa_clause_bug)] = .{ + .llvm_name = "nsa-clause-bug", + .description = "MIMG-NSA in a hard clause has unpredictable results on GFX10.1", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.nsa_encoding)] = .{ .llvm_name = "nsa-encoding", .description = "Support NSA encoding for image instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.nsa_max_size_13)] = .{ + .llvm_name = "nsa-max-size-13", + .description = "The maximum non-sequential address size in VGPRs.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.nsa_max_size_5)] = .{ + .llvm_name = "nsa-max-size-5", + .description = "The maximum non-sequential address size in VGPRs.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.nsa_to_vmem_bug)] = .{ .llvm_name = "nsa-to-vmem-bug", .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", @@ -558,6 +635,16 @@ pub const all_features = blk: { .description = "Branch offset of 3f hardware bug", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.packed_fp32_ops)] = .{ + .llvm_name = "packed-fp32-ops", + .description = "Support packed fp32 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.packed_tid)] = .{ + .llvm_name = "packed-tid", + .description = "Workitem IDs are packed into v0 at kernel launch", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.pk_fmac_f16_inst)] = .{ .llvm_name = "pk-fmac-f16-inst", .description = "Has v_pk_fmac_f16 instruction", @@ -639,6 +726,7 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .ci_insts, .ds_src2_insts, + .extended_image_insts, .flat_address_space, .fp64, .gfx7_gfx8_gfx9_insts, @@ -657,6 +745,11 @@ pub const all_features = blk: { .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.shader_cycles_register)] = .{ + .llvm_name = "shader-cycles-register", + .description = "Has SHADER_CYCLES hardware register", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.si_scheduler)] = .{ .llvm_name = "si-scheduler", .description = "Enable SI Machine Scheduler", @@ -672,6 +765,7 @@ pub const all_features = blk: { .description = "SOUTHERN_ISLANDS GPU generation", .dependencies = featureSet(&[_]Feature{ .ds_src2_insts, + .extended_image_insts, .fp64, .ldsbankcount32, .localmemorysize32768, @@ -693,6 +787,11 @@ pub const all_features = blk: { .description = "Hardware supports SRAMECC", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.tgsplit)] = .{ + .llvm_name = "tgsplit", + .description = "Enable threadgroup split execution", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.trap_handler)] = .{ .llvm_name = "trap-handler", .description = "Trap handler support", @@ -761,6 +860,7 @@ pub const all_features = blk: { .ci_insts, .dpp, .ds_src2_insts, + .extended_image_insts, .fast_denormal_f32, .flat_address_space, .fp64, @@ -892,10 +992,12 @@ pub const cpu = struct { .lds_misaligned_bug, .ldsbankcount32, .mad_mac_f32_insts, + .negative_unaligned_scratch_offset_bug, + .nsa_clause_bug, .nsa_encoding, + .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, - .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -916,6 +1018,7 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .dot7_insts, .ds_src2_insts, .flat_segment_offset_bug, .get_wave_id_inst, @@ -925,10 +1028,12 @@ pub const cpu = struct { .lds_misaligned_bug, .ldsbankcount32, .mad_mac_f32_insts, + .negative_unaligned_scratch_offset_bug, + .nsa_clause_bug, .nsa_encoding, + .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, - .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -949,6 +1054,7 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .dot7_insts, .ds_src2_insts, .flat_segment_offset_bug, .get_wave_id_inst, @@ -958,10 +1064,44 @@ pub const cpu = struct { .lds_misaligned_bug, .ldsbankcount32, .mad_mac_f32_insts, + .negative_unaligned_scratch_offset_bug, + .nsa_clause_bug, .nsa_encoding, + .nsa_max_size_5, + .nsa_to_vmem_bug, + .offset_3f_bug, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .smem_to_vector_write_hazard, + .vcmpx_exec_war_hazard, + .vcmpx_permlane_hazard, + .vmem_to_scalar_write_hazard, + .wavefrontsize32, + .xnack_support, + }), + }; + pub const gfx1013 = CpuModel{ + .name = "gfx1013", + .llvm_name = "gfx1013", + .features = featureSet(&[_]Feature{ + .dl_insts, + .ds_src2_insts, + .flat_segment_offset_bug, + .get_wave_id_inst, + .gfx10, + .gfx10_a_encoding, + .inst_fwd_prefetch_bug, + .lds_branch_vmem_war_hazard, + .lds_misaligned_bug, + .ldsbankcount32, + .mad_mac_f32_insts, + .negative_unaligned_scratch_offset_bug, + .nsa_clause_bug, + .nsa_encoding, + .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, - .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -982,11 +1122,15 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .dot7_insts, .gfx10, .gfx10_3_insts, + .gfx10_a_encoding, .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, + .nsa_max_size_13, + .shader_cycles_register, .wavefrontsize32, }), }; @@ -999,11 +1143,15 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .dot7_insts, .gfx10, .gfx10_3_insts, + .gfx10_a_encoding, .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, + .nsa_max_size_13, + .shader_cycles_register, .wavefrontsize32, }), }; @@ -1016,11 +1164,15 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .dot7_insts, .gfx10, .gfx10_3_insts, + .gfx10_a_encoding, .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, + .nsa_max_size_13, + .shader_cycles_register, .wavefrontsize32, }), }; @@ -1033,11 +1185,57 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .dot7_insts, + .gfx10, + .gfx10_3_insts, + .gfx10_a_encoding, + .gfx10_b_encoding, + .ldsbankcount32, + .nsa_encoding, + .nsa_max_size_13, + .shader_cycles_register, + .wavefrontsize32, + }), + }; + pub const gfx1034 = CpuModel{ + .name = "gfx1034", + .llvm_name = "gfx1034", + .features = featureSet(&[_]Feature{ + .dl_insts, + .dot1_insts, + .dot2_insts, + .dot5_insts, + .dot6_insts, + .dot7_insts, .gfx10, .gfx10_3_insts, + .gfx10_a_encoding, .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, + .nsa_max_size_13, + .shader_cycles_register, + .wavefrontsize32, + }), + }; + pub const gfx1035 = CpuModel{ + .name = "gfx1035", + .llvm_name = "gfx1035", + .features = featureSet(&[_]Feature{ + .dl_insts, + .dot1_insts, + .dot2_insts, + .dot5_insts, + .dot6_insts, + .dot7_insts, + .gfx10, + .gfx10_3_insts, + .gfx10_a_encoding, + .gfx10_b_encoding, + .ldsbankcount32, + .nsa_encoding, + .nsa_max_size_13, + .shader_cycles_register, .wavefrontsize32, }), }; @@ -1171,9 +1369,12 @@ pub const cpu = struct { .name = "gfx900", .llvm_name = "gfx900", .features = featureSet(&[_]Feature{ + .ds_src2_insts, + .extended_image_insts, .gfx9, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, .mad_mix_insts, }), }; @@ -1181,9 +1382,12 @@ pub const cpu = struct { .name = "gfx902", .llvm_name = "gfx902", .features = featureSet(&[_]Feature{ + .ds_src2_insts, + .extended_image_insts, .gfx9, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, .mad_mix_insts, }), }; @@ -1191,10 +1395,13 @@ pub const cpu = struct { .name = "gfx904", .llvm_name = "gfx904", .features = featureSet(&[_]Feature{ + .ds_src2_insts, + .extended_image_insts, .fma_mix_insts, .gfx9, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, }), }; pub const gfx906 = CpuModel{ @@ -1204,11 +1411,15 @@ pub const cpu = struct { .dl_insts, .dot1_insts, .dot2_insts, + .dot7_insts, + .ds_src2_insts, + .extended_image_insts, .fma_mix_insts, .gfx9, .half_rate_64_ops, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, .sramecc_support, }), }; @@ -1224,11 +1435,15 @@ pub const cpu = struct { .dot4_insts, .dot5_insts, .dot6_insts, + .dot7_insts, + .ds_src2_insts, + .extended_image_insts, .fma_mix_insts, .gfx9, .half_rate_64_ops, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, .mai_insts, .mfma_inline_literal_bug, .pk_fmac_f16_inst, @@ -1239,21 +1454,53 @@ pub const cpu = struct { .name = "gfx909", .llvm_name = "gfx909", .features = featureSet(&[_]Feature{ + .ds_src2_insts, + .extended_image_insts, .gfx9, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, .mad_mix_insts, }), }; + pub const gfx90a = CpuModel{ + .name = "gfx90a", + .llvm_name = "gfx90a", + .features = featureSet(&[_]Feature{ + .atomic_fadd_insts, + .dl_insts, + .dot1_insts, + .dot2_insts, + .dot3_insts, + .dot4_insts, + .dot5_insts, + .dot6_insts, + .dot7_insts, + .dpp_64bit, + .fma_mix_insts, + .full_rate_64_ops, + .gfx9, + .gfx90a_insts, + .ldsbankcount32, + .mad_mac_f32_insts, + .mai_insts, + .packed_fp32_ops, + .packed_tid, + .pk_fmac_f16_inst, + .sramecc_support, + }), + }; pub const gfx90c = CpuModel{ .name = "gfx90c", .llvm_name = "gfx90c", .features = featureSet(&[_]Feature{ + .ds_src2_insts, + .extended_image_insts, .gfx9, .image_gather4_d16_bug, .ldsbankcount32, + .mad_mac_f32_insts, .mad_mix_insts, - .xnack, }), }; pub const hainan = CpuModel{ diff --git a/lib/std/target/arc.zig b/lib/std/target/arc.zig new file mode 100644 index 0000000000..822104b466 --- /dev/null +++ b/lib/std/target/arc.zig @@ -0,0 +1,39 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + norm, +}; + +pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet; +pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).Enum.fields.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@enumToInt(Feature.norm)] = .{ + .llvm_name = "norm", + .description = "Enable support for norm instruction.", + .dependencies = featureSet(&[_]Feature{}), + }; + const ti = @typeInfo(Feature); + for (result) |*elem, i| { + elem.index = i; + elem.name = ti.Enum.fields[i].name; + } + break :blk result; +}; + +pub const cpu = struct { + pub const generic = CpuModel{ + .name = "generic", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{}), + }; +}; diff --git a/lib/std/target/arm.zig b/lib/std/target/arm.zig index 394ba05638..42e5f3bfdb 100644 --- a/lib/std/target/arm.zig +++ b/lib/std/target/arm.zig @@ -51,6 +51,7 @@ pub const Feature = enum { fuse_aes, fuse_literals, harden_sls_blr, + harden_sls_nocomdat, harden_sls_retbr, has_v4t, has_v5t, @@ -487,6 +488,11 @@ pub const all_features = blk: { .description = "Harden against straight line speculation across indirect calls", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.harden_sls_nocomdat)] = .{ + .llvm_name = "harden-sls-nocomdat", + .description = "Generate thunk code for SLS mitigation in the normal text section", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.harden_sls_retbr)] = .{ .llvm_name = "harden-sls-retbr", .description = "Harden against straight line speculation across RETurn and BranchRegister instructions", @@ -1245,7 +1251,7 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.v8_7a)] = .{ .llvm_name = "armv8.7-a", - .description = "ARMv86a architecture", + .description = "ARMv87a architecture", .dependencies = featureSet(&[_]Feature{ .aclass, .crc, @@ -1517,13 +1523,6 @@ pub const cpu = struct { .vfp2, }), }; - pub const arm1176j_s = CpuModel{ - .name = "arm1176j_s", - .llvm_name = "arm1176j-s", - .features = featureSet(&[_]Feature{ - .v6kz, - }), - }; pub const arm1176jz_s = CpuModel{ .name = "arm1176jz_s", .llvm_name = "arm1176jz-s", @@ -1889,6 +1888,7 @@ pub const cpu = struct { .name = "cortex_m0", .llvm_name = "cortex-m0", .features = featureSet(&[_]Feature{ + .no_branch_predictor, .v6m, }), }; @@ -1896,6 +1896,7 @@ pub const cpu = struct { .name = "cortex_m0plus", .llvm_name = "cortex-m0plus", .features = featureSet(&[_]Feature{ + .no_branch_predictor, .v6m, }), }; @@ -1903,6 +1904,7 @@ pub const cpu = struct { .name = "cortex_m1", .llvm_name = "cortex-m1", .features = featureSet(&[_]Feature{ + .no_branch_predictor, .v6m, }), }; @@ -1910,6 +1912,7 @@ pub const cpu = struct { .name = "cortex_m23", .llvm_name = "cortex-m23", .features = featureSet(&[_]Feature{ + .no_branch_predictor, .no_movt, .v8m, }), @@ -2225,6 +2228,7 @@ pub const cpu = struct { .name = "sc000", .llvm_name = "sc000", .features = featureSet(&[_]Feature{ + .no_branch_predictor, .v6m, }), }; diff --git a/lib/std/target/hexagon.zig b/lib/std/target/hexagon.zig index a9922e2866..de0e34aa3d 100644 --- a/lib/std/target/hexagon.zig +++ b/lib/std/target/hexagon.zig @@ -16,6 +16,7 @@ pub const Feature = enum { hvxv65, hvxv66, hvxv67, + hvxv68, long_calls, mem_noshuf, memops, @@ -35,6 +36,7 @@ pub const Feature = enum { v65, v66, v67, + v68, zreg, }; @@ -117,6 +119,13 @@ pub const all_features = blk: { .hvxv66, }), }; + result[@enumToInt(Feature.hvxv68)] = .{ + .llvm_name = "hvxv68", + .description = "Hexagon HVX instructions", + .dependencies = featureSet(&[_]Feature{ + .hvxv67, + }), + }; result[@enumToInt(Feature.long_calls)] = .{ .llvm_name = "long-calls", .description = "Use constant-extended calls", @@ -216,6 +225,11 @@ pub const all_features = blk: { .description = "Enable Hexagon V67 architecture", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.v68)] = .{ + .llvm_name = "v68", + .description = "Enable Hexagon V68 architecture", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.zreg)] = .{ .llvm_name = "zreg", .description = "Hexagon ZReg extension instructions", @@ -385,4 +399,25 @@ pub const cpu = struct { .v67, }), }; + pub const hexagonv68 = CpuModel{ + .name = "hexagonv68", + .llvm_name = "hexagonv68", + .features = featureSet(&[_]Feature{ + .compound, + .duplex, + .mem_noshuf, + .memops, + .nvj, + .nvs, + .small_data, + .v5, + .v55, + .v60, + .v62, + .v65, + .v66, + .v67, + .v68, + }), + }; }; diff --git a/lib/std/target/nvptx.zig b/lib/std/target/nvptx.zig index d4eb0f4e3f..0a5581090e 100644 --- a/lib/std/target/nvptx.zig +++ b/lib/std/target/nvptx.zig @@ -17,6 +17,8 @@ pub const Feature = enum { ptx64, ptx65, ptx70, + ptx71, + ptx72, sm_20, sm_21, sm_30, @@ -33,6 +35,7 @@ pub const Feature = enum { sm_72, sm_75, sm_80, + sm_86, }; pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet; @@ -104,6 +107,16 @@ pub const all_features = blk: { .description = "Use PTX version 7.0", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.ptx71)] = .{ + .llvm_name = "ptx71", + .description = "Use PTX version 7.1", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.ptx72)] = .{ + .llvm_name = "ptx72", + .description = "Use PTX version 7.2", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.sm_20)] = .{ .llvm_name = "sm_20", .description = "Target SM 2.0", @@ -184,6 +197,11 @@ pub const all_features = blk: { .description = "Target SM 8.0", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.sm_86)] = .{ + .llvm_name = "sm_86", + .description = "Target SM 8.6", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (result) |*elem, i| { elem.index = i; @@ -317,4 +335,12 @@ pub const cpu = struct { .sm_80, }), }; + pub const sm_86 = CpuModel{ + .name = "sm_86", + .llvm_name = "sm_86", + .features = featureSet(&[_]Feature{ + .ptx71, + .sm_86, + }), + }; }; diff --git a/lib/std/target/powerpc.zig b/lib/std/target/powerpc.zig index 6fc05a2379..3145b2b14c 100644 --- a/lib/std/target/powerpc.zig +++ b/lib/std/target/powerpc.zig @@ -37,6 +37,7 @@ pub const Feature = enum { htm, icbt, invariant_function_descriptors, + isa_v207_instructions, isa_v30_instructions, isa_v31_instructions, isel, @@ -62,7 +63,10 @@ pub const Feature = enum { ppc_prera_sched, predictable_select_expensive, prefix_instrs, + privileged, + quadword_atomics, recipprec, + rop_protect, secure_plt, slow_popcntd, spe, @@ -277,10 +281,17 @@ pub const all_features = blk: { .description = "Assume function descriptors are invariant", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.isa_v207_instructions)] = .{ + .llvm_name = "isa-v207-instructions", + .description = "Enable instructions in ISA 2.07.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.isa_v30_instructions)] = .{ .llvm_name = "isa-v30-instructions", .description = "Enable instructions in ISA 3.0.", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .isa_v207_instructions, + }), }; result[@enumToInt(Feature.isa_v31_instructions)] = .{ .llvm_name = "isa-v31-instructions", @@ -433,11 +444,26 @@ pub const all_features = blk: { .power9_altivec, }), }; + result[@enumToInt(Feature.privileged)] = .{ + .llvm_name = "privileged", + .description = "Add privileged instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.quadword_atomics)] = .{ + .llvm_name = "quadword-atomics", + .description = "Enable lqarx and stqcx.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.recipprec)] = .{ .llvm_name = "recipprec", .description = "Assume higher precision reciprocal estimates", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.rop_protect)] = .{ + .llvm_name = "rop-protect", + .description = "Add ROP protect", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.secure_plt)] = .{ .llvm_name = "secure-plt", .description = "Enable secure plt mode", @@ -696,6 +722,7 @@ pub const cpu = struct { .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, + .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, @@ -790,6 +817,7 @@ pub const cpu = struct { .fuse_addis_load, .htm, .icbt, + .isa_v207_instructions, .isel, .ldbrx, .lfiwax, @@ -798,6 +826,7 @@ pub const cpu = struct { .popcntd, .power8_vector, .predictable_select_expensive, + .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, @@ -837,6 +866,7 @@ pub const cpu = struct { .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, + .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, @@ -989,6 +1019,7 @@ pub const cpu = struct { .fuse_addis_load, .htm, .icbt, + .isa_v207_instructions, .isel, .ldbrx, .lfiwax, @@ -997,6 +1028,7 @@ pub const cpu = struct { .popcntd, .power8_vector, .predictable_select_expensive, + .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, @@ -1033,6 +1065,7 @@ pub const cpu = struct { .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, + .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig index 28c6bdc366..70a8f73245 100644 --- a/lib/std/target/riscv.zig +++ b/lib/std/target/riscv.zig @@ -185,7 +185,7 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.experimental_zvamo)] = .{ .llvm_name = "experimental-zvamo", - .description = "'Zvamo'(Vector AMO Operations)", + .description = "'Zvamo' (Vector AMO Operations)", .dependencies = featureSet(&[_]Feature{ .experimental_v, }), diff --git a/lib/std/target/systemz.zig b/lib/std/target/systemz.zig index 566a6de333..be97570629 100644 --- a/lib/std/target/systemz.zig +++ b/lib/std/target/systemz.zig @@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { + bear_enhancement, deflate_conversion, dfp_packed_conversion, dfp_zoned_conversion, @@ -31,8 +32,11 @@ pub const Feature = enum { miscellaneous_extensions, miscellaneous_extensions_2, miscellaneous_extensions_3, + nnp_assist, population_count, + processor_activity_instrumentation, processor_assist, + reset_dat_protection, reset_reference_bits_multiple, soft_float, transactional_execution, @@ -41,6 +45,7 @@ pub const Feature = enum { vector_enhancements_2, vector_packed_decimal, vector_packed_decimal_enhancement, + vector_packed_decimal_enhancement_2, }; pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet; @@ -52,6 +57,11 @@ pub const all_features = blk: { const len = @typeInfo(Feature).Enum.fields.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; + result[@enumToInt(Feature.bear_enhancement)] = .{ + .llvm_name = "bear-enhancement", + .description = "Assume that the BEAR-enhancement facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.deflate_conversion)] = .{ .llvm_name = "deflate-conversion", .description = "Assume that the deflate-conversion facility is installed", @@ -182,16 +192,31 @@ pub const all_features = blk: { .description = "Assume that the miscellaneous-extensions facility 3 is installed", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.nnp_assist)] = .{ + .llvm_name = "nnp-assist", + .description = "Assume that the NNP-assist facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.population_count)] = .{ .llvm_name = "population-count", .description = "Assume that the population-count facility is installed", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.processor_activity_instrumentation)] = .{ + .llvm_name = "processor-activity-instrumentation", + .description = "Assume that the processor-activity-instrumentation facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.processor_assist)] = .{ .llvm_name = "processor-assist", .description = "Assume that the processor-assist facility is installed", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.reset_dat_protection)] = .{ + .llvm_name = "reset-dat-protection", + .description = "Assume that the reset-DAT-protection facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.reset_reference_bits_multiple)] = .{ .llvm_name = "reset-reference-bits-multiple", .description = "Assume that the reset-reference-bits-multiple facility is installed", @@ -232,6 +257,11 @@ pub const all_features = blk: { .description = "Assume that the vector packed decimal enhancement facility is installed", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.vector_packed_decimal_enhancement_2)] = .{ + .llvm_name = "vector-packed-decimal-enhancement-2", + .description = "Assume that the vector packed decimal enhancement facility 2 is installed", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (result) |*elem, i| { elem.index = i; @@ -368,6 +398,52 @@ pub const cpu = struct { .vector_packed_decimal_enhancement, }), }; + pub const arch14 = CpuModel{ + .name = "arch14", + .llvm_name = "arch14", + .features = featureSet(&[_]Feature{ + .bear_enhancement, + .deflate_conversion, + .dfp_packed_conversion, + .dfp_zoned_conversion, + .distinct_ops, + .enhanced_dat_2, + .enhanced_sort, + .execution_hint, + .fast_serialization, + .fp_extension, + .guarded_storage, + .high_word, + .insert_reference_bits_multiple, + .interlocked_access1, + .load_and_trap, + .load_and_zero_rightmost_byte, + .load_store_on_cond, + .load_store_on_cond_2, + .message_security_assist_extension3, + .message_security_assist_extension4, + .message_security_assist_extension5, + .message_security_assist_extension7, + .message_security_assist_extension8, + .message_security_assist_extension9, + .miscellaneous_extensions, + .miscellaneous_extensions_2, + .miscellaneous_extensions_3, + .nnp_assist, + .population_count, + .processor_activity_instrumentation, + .processor_assist, + .reset_dat_protection, + .reset_reference_bits_multiple, + .transactional_execution, + .vector, + .vector_enhancements_1, + .vector_enhancements_2, + .vector_packed_decimal, + .vector_packed_decimal_enhancement, + .vector_packed_decimal_enhancement_2, + }), + }; pub const arch8 = CpuModel{ .name = "arch8", .llvm_name = "arch8", diff --git a/lib/std/target/wasm.zig b/lib/std/target/wasm.zig index ac14ac318b..f120dfd7a5 100644 --- a/lib/std/target/wasm.zig +++ b/lib/std/target/wasm.zig @@ -15,7 +15,6 @@ pub const Feature = enum { sign_ext, simd128, tail_call, - unimplemented_simd128, }; pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet; @@ -77,13 +76,6 @@ pub const all_features = blk: { .description = "Enable tail call instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.unimplemented_simd128)] = .{ - .llvm_name = "unimplemented-simd128", - .description = "Enable 128-bit SIMD not yet implemented in engines", - .dependencies = featureSet(&[_]Feature{ - .simd128, - }), - }; const ti = @typeInfo(Feature); for (result) |*elem, i| { elem.index = i; diff --git a/lib/std/target/x86.zig b/lib/std/target/x86.zig index 5c57831bd5..c0a64c1077 100644 --- a/lib/std/target/x86.zig +++ b/lib/std/target/x86.zig @@ -55,10 +55,12 @@ pub const Feature = enum { fast_gather, fast_hops, fast_lzcnt, + fast_movbe, fast_scalar_fsqrt, fast_scalar_shift_masks, fast_shld_rotate, - fast_variable_shuffle, + fast_variable_crosslane_shuffle, + fast_variable_perlane_shuffle, fast_vector_fsqrt, fast_vector_shift_masks, fma, @@ -458,6 +460,11 @@ pub const all_features = blk: { .description = "LZCNT instructions are as fast as most simple integer ops", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.fast_movbe)] = .{ + .llvm_name = "fast-movbe", + .description = "Prefer a movbe over a single-use load + bswap / single-use bswap + store", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.fast_scalar_fsqrt)] = .{ .llvm_name = "fast-scalar-fsqrt", .description = "Scalar SQRT is fast (disable Newton-Raphson)", @@ -473,9 +480,14 @@ pub const all_features = blk: { .description = "SHLD can be used as a faster rotate", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.fast_variable_shuffle)] = .{ - .llvm_name = "fast-variable-shuffle", - .description = "Shuffles with variable masks are fast", + result[@enumToInt(Feature.fast_variable_crosslane_shuffle)] = .{ + .llvm_name = "fast-variable-crosslane-shuffle", + .description = "Cross-lane shuffles with variable masks are fast", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.fast_variable_perlane_shuffle)] = .{ + .llvm_name = "fast-variable-perlane-shuffle", + .description = "Per-lane shuffles with variable masks are fast", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.fast_vector_fsqrt)] = .{ @@ -1010,26 +1022,27 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .adx, - .aes, .avxvnni, .bmi, .bmi2, .cldemote, .clflushopt, + .clwb, .cmov, .cx16, - .ermsb, .f16c, .false_deps_popcnt, .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fma, .fsgsbase, .fxsr, + .gfni, .hreset, .idivq_to_divl, .invpcid, @@ -1037,19 +1050,27 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .movdir64b, + .movdiri, .nopl, - .pclmul, + .pconfig, + .pku, .popcnt, .prfchw, .ptwrite, + .rdpid, .rdrnd, .rdseed, .sahf, .serialize, - .sgx, + .sha, + .shstk, .slow_3ops_lea, + .vaes, + .vpclmulqdq, .vzeroupper, .waitpkg, + .widekl, .x87, .xsavec, .xsaveopt, @@ -1292,6 +1313,7 @@ pub const cpu = struct { .f16c, .fast_11bytenop, .fast_bextr, + .fast_movbe, .fast_scalar_shift_masks, .fma, .fxsr, @@ -1324,6 +1346,7 @@ pub const cpu = struct { .f16c, .fast_11bytenop, .fast_bextr, + .fast_movbe, .fast_scalar_shift_masks, .fma, .fsgsbase, @@ -1359,6 +1382,7 @@ pub const cpu = struct { .f16c, .fast_11bytenop, .fast_bextr, + .fast_movbe, .fast_scalar_shift_masks, .fma, .fsgsbase, @@ -1424,7 +1448,8 @@ pub const cpu = struct { .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fma, .fsgsbase, .fxsr, @@ -1485,6 +1510,7 @@ pub const cpu = struct { .fast_bextr, .fast_hops, .fast_lzcnt, + .fast_movbe, .fast_scalar_shift_masks, .fast_vector_shift_masks, .fxsr, @@ -1548,7 +1574,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fxsr, @@ -1567,7 +1594,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .sha, .slow_3ops_lea, .vzeroupper, @@ -1601,7 +1627,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fxsr, @@ -1652,7 +1679,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fxsr, @@ -1714,7 +1742,8 @@ pub const cpu = struct { .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fma, .fsgsbase, .fxsr, @@ -1844,6 +1873,7 @@ pub const cpu = struct { .cmov, .cx16, .false_deps_popcnt, + .fast_movbe, .fsgsbase, .fxsr, .mmx, @@ -1877,6 +1907,7 @@ pub const cpu = struct { .clflushopt, .cmov, .cx16, + .fast_movbe, .fsgsbase, .fxsr, .mmx, @@ -1890,7 +1921,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .sha, .slow_incdec, .slow_lea, @@ -1921,7 +1951,8 @@ pub const cpu = struct { .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fma, .fsgsbase, .fxsr, @@ -1960,7 +1991,6 @@ pub const cpu = struct { .bmi, .bmi2, .clflushopt, - .clwb, .cmov, .cx16, .ermsb, @@ -1968,7 +1998,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fsrm, @@ -1989,7 +2020,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .sha, .slow_3ops_lea, .vaes, @@ -2027,7 +2057,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fsrm, @@ -2049,7 +2080,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .sha, .slow_3ops_lea, .vaes, @@ -2175,6 +2205,7 @@ pub const cpu = struct { .cmov, .cx16, .fast_gather, + .fast_movbe, .fsgsbase, .fxsr, .idivq_to_divl, @@ -2214,6 +2245,7 @@ pub const cpu = struct { .cmov, .cx16, .fast_gather, + .fast_movbe, .fsgsbase, .fxsr, .idivq_to_divl, @@ -2472,6 +2504,64 @@ pub const cpu = struct { .x87, }), }; + pub const rocketlake = CpuModel{ + .name = "rocketlake", + .llvm_name = "rocketlake", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .avx512bitalg, + .avx512cd, + .avx512dq, + .avx512ifma, + .avx512vbmi, + .avx512vbmi2, + .avx512vl, + .avx512vnni, + .avx512vpopcntdq, + .bmi, + .bmi2, + .clflushopt, + .cmov, + .cx16, + .ermsb, + .fast_15bytenop, + .fast_gather, + .fast_scalar_fsqrt, + .fast_shld_rotate, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fsgsbase, + .fsrm, + .fxsr, + .gfni, + .idivq_to_divl, + .invpcid, + .lzcnt, + .macrofusion, + .mmx, + .movbe, + .nopl, + .pku, + .popcnt, + .prefer_256_bit, + .prfchw, + .rdpid, + .rdrnd, + .rdseed, + .sahf, + .sha, + .slow_3ops_lea, + .vaes, + .vpclmulqdq, + .vzeroupper, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; pub const sandybridge = CpuModel{ .name = "sandybridge", .llvm_name = "sandybridge", @@ -2532,7 +2622,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fsrm, @@ -2558,7 +2649,6 @@ pub const cpu = struct { .rdseed, .sahf, .serialize, - .sgx, .sha, .shstk, .slow_3ops_lea, @@ -2584,6 +2674,7 @@ pub const cpu = struct { .cx16, .false_deps_popcnt, .fast_7bytenop, + .fast_movbe, .fxsr, .idivq_to_divl, .mmx, @@ -2626,7 +2717,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fxsr, @@ -2673,7 +2765,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fma, .fsgsbase, @@ -2691,7 +2784,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .slow_3ops_lea, .vzeroupper, .x87, @@ -2723,7 +2815,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fxsr, @@ -2759,6 +2852,7 @@ pub const cpu = struct { .cx16, .false_deps_popcnt, .fast_7bytenop, + .fast_movbe, .fxsr, .idivq_to_divl, .mmx, @@ -2805,7 +2899,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fsgsbase, .fsrm, @@ -2828,7 +2923,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .sha, .shstk, .slow_3ops_lea, @@ -2851,6 +2945,7 @@ pub const cpu = struct { .clwb, .cmov, .cx16, + .fast_movbe, .fsgsbase, .fxsr, .gfni, @@ -2865,7 +2960,6 @@ pub const cpu = struct { .rdrnd, .rdseed, .sahf, - .sgx, .sha, .slow_incdec, .slow_lea, @@ -2978,7 +3072,8 @@ pub const cpu = struct { .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fma, .fxsr, .idivq_to_divl, @@ -3013,7 +3108,8 @@ pub const cpu = struct { .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, - .fast_variable_shuffle, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, .fast_vector_fsqrt, .fxsr, .idivq_to_divl, @@ -3065,6 +3161,7 @@ pub const cpu = struct { .fast_15bytenop, .fast_bextr, .fast_lzcnt, + .fast_movbe, .fast_scalar_shift_masks, .fma, .fsgsbase, @@ -3110,6 +3207,7 @@ pub const cpu = struct { .fast_15bytenop, .fast_bextr, .fast_lzcnt, + .fast_movbe, .fast_scalar_shift_masks, .fma, .fsgsbase, @@ -3156,13 +3254,16 @@ pub const cpu = struct { .fast_15bytenop, .fast_bextr, .fast_lzcnt, + .fast_movbe, .fast_scalar_shift_masks, + .fast_variable_perlane_shuffle, .fma, .fsgsbase, .fsrm, .fxsr, .invpcid, .lzcnt, + .macrofusion, .mmx, .movbe, .mwaitx, -- cgit v1.2.3 From 2f599b655b81004f101773b3b35dc112c0d84b72 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Mon, 16 Aug 2021 01:11:10 -0700 Subject: update src/ to LLVM 13 rc1 API --- lib/std/target.zig | 7 + src/clang.zig | 79 ++++++- src/codegen/llvm.zig | 3 + src/codegen/llvm/bindings.zig | 2 + src/stage1/codegen.cpp | 39 ++-- src/stage1/target.cpp | 8 +- src/target.zig | 5 + src/zig_clang.cpp | 514 +++++++++++++++++++++++++++--------------- src/zig_clang.h | 79 ++++++- src/zig_llvm.cpp | 79 +------ src/zig_llvm.h | 28 +-- 11 files changed, 542 insertions(+), 301 deletions(-) (limited to 'lib/std') diff --git a/lib/std/target.zig b/lib/std/target.zig index 69800c9f8b..a5a82cbe09 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -464,6 +464,7 @@ pub const Target = struct { musl, musleabi, musleabihf, + muslx32, msvc, itanium, cygnus, @@ -758,6 +759,7 @@ pub const Target = struct { bpfeb, csky, hexagon, + m68k, mips, mipsel, mips64, @@ -900,6 +902,7 @@ pub const Target = struct { .arm => ._ARM, .armeb => ._ARM, .hexagon => ._HEXAGON, + .m68k => ._68K, .le32 => ._NONE, .mips => ._MIPS, .mipsel => ._MIPS_RS3_LE, @@ -960,6 +963,7 @@ pub const Target = struct { .arm => .ARM, .armeb => .Unknown, .hexagon => .Unknown, + .m68k => .Unknown, .le32 => .Unknown, .mips => .Unknown, .mipsel => .Unknown, @@ -1063,6 +1067,7 @@ pub const Target = struct { .armeb, .aarch64_be, .bpfeb, + .m68k, .mips, .mips64, .powerpc, @@ -1089,6 +1094,7 @@ pub const Target = struct { .armeb, .csky, .hexagon, + .m68k, .le32, .mips, .mipsel, @@ -1587,6 +1593,7 @@ pub const Target = struct { .arc, .csky, .hexagon, + .m68k, .msp430, .r600, .amdgcn, diff --git a/src/clang.zig b/src/clang.zig index 1254a505f4..430c9093f2 100644 --- a/src/clang.zig +++ b/src/clang.zig @@ -1168,13 +1168,16 @@ const StmtClass = enum(c_int) { IndirectGotoStmtClass, MSDependentExistsStmtClass, NullStmtClass, + OMPCanonicalLoopClass, OMPAtomicDirectiveClass, OMPBarrierDirectiveClass, OMPCancelDirectiveClass, OMPCancellationPointDirectiveClass, OMPCriticalDirectiveClass, OMPDepobjDirectiveClass, + OMPDispatchDirectiveClass, OMPFlushDirectiveClass, + OMPInteropDirectiveClass, OMPDistributeDirectiveClass, OMPDistributeParallelForDirectiveClass, OMPDistributeParallelForSimdDirectiveClass, @@ -1200,6 +1203,9 @@ const StmtClass = enum(c_int) { OMPTeamsDistributeParallelForDirectiveClass, OMPTeamsDistributeParallelForSimdDirectiveClass, OMPTeamsDistributeSimdDirectiveClass, + OMPTileDirectiveClass, + OMPUnrollDirectiveClass, + OMPMaskedDirectiveClass, OMPMasterDirectiveClass, OMPOrderedDirectiveClass, OMPParallelDirectiveClass, @@ -1348,6 +1354,7 @@ const StmtClass = enum(c_int) { PseudoObjectExprClass, RecoveryExprClass, RequiresExprClass, + SYCLUniqueStableNameExprClass, ShuffleVectorExprClass, SizeOfPackExprClass, SourceLocExprClass, @@ -1390,6 +1397,7 @@ pub const CK = enum(c_int) { PointerToIntegral, PointerToBoolean, ToVoid, + MatrixCast, VectorSplat, IntegralCast, IntegralToBoolean, @@ -1445,6 +1453,8 @@ pub const DeclKind = enum(c_int) { Import, LifetimeExtendedTemporary, LinkageSpec, + Using, + UsingEnum, Label, Namespace, NamespaceAlias, @@ -1473,7 +1483,7 @@ pub const DeclKind = enum(c_int) { TypeAlias, Typedef, UnresolvedUsingTypename, - Using, + UnresolvedUsingIfExists, UsingDirective, UsingPack, UsingShadow, @@ -1615,6 +1625,72 @@ pub const BuiltinTypeKind = enum(c_int) { SveBool, VectorQuad, VectorPair, + RvvInt8mf8, + RvvInt8mf4, + RvvInt8mf2, + RvvInt8m1, + RvvInt8m2, + RvvInt8m4, + RvvInt8m8, + RvvUint8mf8, + RvvUint8mf4, + RvvUint8mf2, + RvvUint8m1, + RvvUint8m2, + RvvUint8m4, + RvvUint8m8, + RvvInt16mf4, + RvvInt16mf2, + RvvInt16m1, + RvvInt16m2, + RvvInt16m4, + RvvInt16m8, + RvvUint16mf4, + RvvUint16mf2, + RvvUint16m1, + RvvUint16m2, + RvvUint16m4, + RvvUint16m8, + RvvInt32mf2, + RvvInt32m1, + RvvInt32m2, + RvvInt32m4, + RvvInt32m8, + RvvUint32mf2, + RvvUint32m1, + RvvUint32m2, + RvvUint32m4, + RvvUint32m8, + RvvInt64m1, + RvvInt64m2, + RvvInt64m4, + RvvInt64m8, + RvvUint64m1, + RvvUint64m2, + RvvUint64m4, + RvvUint64m8, + RvvFloat16mf4, + RvvFloat16mf2, + RvvFloat16m1, + RvvFloat16m2, + RvvFloat16m4, + RvvFloat16m8, + RvvFloat32mf2, + RvvFloat32m1, + RvvFloat32m2, + RvvFloat32m4, + RvvFloat32m8, + RvvFloat64m1, + RvvFloat64m2, + RvvFloat64m4, + RvvFloat64m8, + RvvBool1, + RvvBool2, + RvvBool4, + RvvBool8, + RvvBool16, + RvvBool32, + RvvBool64, Void, Bool, Char_U, @@ -1705,6 +1781,7 @@ pub const CallingConv = enum(c_int) { SpirFunction, OpenCLKernel, Swift, + SwiftAsync, PreserveMost, PreserveAll, AArch64VectorCall, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 4f9a24f80c..2b678b0a69 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -31,6 +31,7 @@ pub fn targetTriple(allocator: *Allocator, target: std.Target) ![:0]u8 { .bpfeb => "bpfeb", .csky => "csky", .hexagon => "hexagon", + .m68k => "m68k", .mips => "mips", .mipsel => "mipsel", .mips64 => "mips64", @@ -140,6 +141,7 @@ pub fn targetTriple(allocator: *Allocator, target: std.Target) ![:0]u8 { .musl => "musl", .musleabi => "musleabi", .musleabihf => "musleabihf", + .muslx32 => "muslx32", .msvc => "msvc", .itanium => "itanium", .cygnus => "cygnus", @@ -1463,6 +1465,7 @@ pub const FuncGen = struct { llvm.Bool.fromBool(is_volatile), .False, .ATT, + .False, ); return self.builder.buildCall( asm_fn, diff --git a/src/codegen/llvm/bindings.zig b/src/codegen/llvm/bindings.zig index da02e56ac8..fc97dfb81f 100644 --- a/src/codegen/llvm/bindings.zig +++ b/src/codegen/llvm/bindings.zig @@ -259,6 +259,7 @@ extern fn LLVMGetInlineAsm( HasSideEffects: Bool, IsAlignStack: Bool, Dialect: InlineAsmDialect, + CanThrow: Bool, ) *const Value; pub const functionType = LLVMFunctionType; @@ -840,6 +841,7 @@ pub const ArchType = enum(c_int) { bpfeb, csky, hexagon, + m68k, mips, mipsel, mips64, diff --git a/src/stage1/codegen.cpp b/src/stage1/codegen.cpp index 359af18e82..063671b1bf 100644 --- a/src/stage1/codegen.cpp +++ b/src/stage1/codegen.cpp @@ -3953,7 +3953,7 @@ static LLVMValueRef gen_valgrind_client_request(CodeGen *g, LLVMValueRef default input_and_output_count, false); LLVMValueRef asm_fn = LLVMGetInlineAsm(function_type, buf_ptr(asm_template), buf_len(asm_template), buf_ptr(asm_constraints), buf_len(asm_constraints), asm_has_side_effects, asm_is_alignstack, - LLVMInlineAsmDialectATT); + LLVMInlineAsmDialectATT, false); return LLVMBuildCall(g->builder, asm_fn, param_values, input_and_output_count, ""); } } @@ -5064,7 +5064,7 @@ static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, Stage1A bool is_volatile = instruction->has_side_effects || (asm_expr->output_list.length == 0); LLVMValueRef asm_fn = LLVMGetInlineAsm(function_type, buf_ptr(&llvm_template), buf_len(&llvm_template), - buf_ptr(&constraint_buf), buf_len(&constraint_buf), is_volatile, false, LLVMInlineAsmDialectATT); + buf_ptr(&constraint_buf), buf_len(&constraint_buf), is_volatile, false, LLVMInlineAsmDialectATT, false); LLVMValueRef built_call = LLVMBuildCall(g->builder, asm_fn, param_values, (unsigned)input_and_output_count, ""); heap::c_allocator.deallocate(param_values, input_and_output_count); @@ -5606,21 +5606,21 @@ static LLVMAtomicOrdering to_LLVMAtomicOrdering(AtomicOrder atomic_order) { zig_unreachable(); } -static enum ZigLLVM_AtomicRMWBinOp to_ZigLLVMAtomicRMWBinOp(AtomicRmwOp op, bool is_signed, bool is_float) { +static LLVMAtomicRMWBinOp to_LLVMAtomicRMWBinOp(AtomicRmwOp op, bool is_signed, bool is_float) { switch (op) { - case AtomicRmwOp_xchg: return ZigLLVMAtomicRMWBinOpXchg; + case AtomicRmwOp_xchg: return LLVMAtomicRMWBinOpXchg; case AtomicRmwOp_add: - return is_float ? ZigLLVMAtomicRMWBinOpFAdd : ZigLLVMAtomicRMWBinOpAdd; + return is_float ? LLVMAtomicRMWBinOpFAdd : LLVMAtomicRMWBinOpAdd; case AtomicRmwOp_sub: - return is_float ? ZigLLVMAtomicRMWBinOpFSub : ZigLLVMAtomicRMWBinOpSub; - case AtomicRmwOp_and: return ZigLLVMAtomicRMWBinOpAnd; - case AtomicRmwOp_nand: return ZigLLVMAtomicRMWBinOpNand; - case AtomicRmwOp_or: return ZigLLVMAtomicRMWBinOpOr; - case AtomicRmwOp_xor: return ZigLLVMAtomicRMWBinOpXor; + return is_float ? LLVMAtomicRMWBinOpFSub : LLVMAtomicRMWBinOpSub; + case AtomicRmwOp_and: return LLVMAtomicRMWBinOpAnd; + case AtomicRmwOp_nand: return LLVMAtomicRMWBinOpNand; + case AtomicRmwOp_or: return LLVMAtomicRMWBinOpOr; + case AtomicRmwOp_xor: return LLVMAtomicRMWBinOpXor; case AtomicRmwOp_max: - return is_signed ? ZigLLVMAtomicRMWBinOpMax : ZigLLVMAtomicRMWBinOpUMax; + return is_signed ? LLVMAtomicRMWBinOpMax : LLVMAtomicRMWBinOpUMax; case AtomicRmwOp_min: - return is_signed ? ZigLLVMAtomicRMWBinOpMin : ZigLLVMAtomicRMWBinOpUMin; + return is_signed ? LLVMAtomicRMWBinOpMin : LLVMAtomicRMWBinOpUMin; } zig_unreachable(); } @@ -5679,8 +5679,9 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, Stage1A LLVMAtomicOrdering success_order = to_LLVMAtomicOrdering(instruction->success_order); LLVMAtomicOrdering failure_order = to_LLVMAtomicOrdering(instruction->failure_order); - LLVMValueRef result_val = ZigLLVMBuildCmpXchg(g->builder, ptr_val, cmp_val, new_val, - success_order, failure_order, instruction->is_weak); + LLVMValueRef result_val = LLVMBuildAtomicCmpXchg(g->builder, ptr_val, cmp_val, new_val, + success_order, failure_order, g->is_single_threaded); + LLVMSetWeak(result_val, instruction->is_weak); ZigType *optional_type = instruction->base.value->type; assert(optional_type->id == ZigTypeIdOptional); @@ -6446,13 +6447,13 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable, } else { is_signed = false; } - enum ZigLLVM_AtomicRMWBinOp op = to_ZigLLVMAtomicRMWBinOp(instruction->op, is_signed, is_float); + LLVMAtomicRMWBinOp op = to_LLVMAtomicRMWBinOp(instruction->op, is_signed, is_float); LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering); LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr); LLVMValueRef operand = ir_llvm_value(g, instruction->operand); LLVMTypeRef actual_abi_type = get_atomic_abi_type(g, instruction->ptr, - op == ZigLLVMAtomicRMWBinOpXchg); + op == LLVMAtomicRMWBinOpXchg); if (actual_abi_type != nullptr) { // operand needs widening and truncating or bitcasting. LLVMValueRef casted_ptr = LLVMBuildBitCast(g->builder, ptr, @@ -6465,7 +6466,7 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable, } else { casted_operand = LLVMBuildZExt(g->builder, operand, actual_abi_type, ""); } - LLVMValueRef uncasted_result = ZigLLVMBuildAtomicRMW(g->builder, op, casted_ptr, casted_operand, ordering, + LLVMValueRef uncasted_result = LLVMBuildAtomicRMW(g->builder, op, casted_ptr, casted_operand, ordering, g->is_single_threaded); if (is_float) { return LLVMBuildBitCast(g->builder, uncasted_result, get_llvm_type(g, operand_type), ""); @@ -6475,14 +6476,14 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable, } if (get_codegen_ptr_type_bail(g, operand_type) == nullptr) { - return ZigLLVMBuildAtomicRMW(g->builder, op, ptr, operand, ordering, g->is_single_threaded); + return LLVMBuildAtomicRMW(g->builder, op, ptr, operand, ordering, g->is_single_threaded); } // it's a pointer but we need to treat it as an int LLVMValueRef casted_ptr = LLVMBuildBitCast(g->builder, ptr, LLVMPointerType(g->builtin_types.entry_usize->llvm_type, 0), ""); LLVMValueRef casted_operand = LLVMBuildPtrToInt(g->builder, operand, g->builtin_types.entry_usize->llvm_type, ""); - LLVMValueRef uncasted_result = ZigLLVMBuildAtomicRMW(g->builder, op, casted_ptr, casted_operand, ordering, + LLVMValueRef uncasted_result = LLVMBuildAtomicRMW(g->builder, op, casted_ptr, casted_operand, ordering, g->is_single_threaded); return LLVMBuildIntToPtr(g->builder, uncasted_result, get_llvm_type(g, operand_type), ""); } diff --git a/src/stage1/target.cpp b/src/stage1/target.cpp index 6594eb57d5..9c95be3d5a 100644 --- a/src/stage1/target.cpp +++ b/src/stage1/target.cpp @@ -25,6 +25,7 @@ static const ZigLLVM_ArchType arch_list[] = { ZigLLVM_bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian) ZigLLVM_csky, // CSKY: csky ZigLLVM_hexagon, // Hexagon: hexagon + ZigLLVM_m68k, // M68k: Motorola 680x0 family ZigLLVM_mips, // MIPS: mips, mipsallegrex, mipsr6 ZigLLVM_mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el ZigLLVM_mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6 @@ -147,6 +148,7 @@ static const ZigLLVM_EnvironmentType abi_list[] = { ZigLLVM_Musl, ZigLLVM_MuslEABI, ZigLLVM_MuslEABIHF, + ZigLLVM_MuslX32, ZigLLVM_MSVC, ZigLLVM_Itanium, @@ -497,6 +499,7 @@ uint32_t target_arch_pointer_bit_width(ZigLLVM_ArchType arch) { case ZigLLVM_arm: case ZigLLVM_armeb: case ZigLLVM_hexagon: + case ZigLLVM_m68k: case ZigLLVM_le32: case ZigLLVM_mips: case ZigLLVM_mipsel: @@ -564,6 +567,7 @@ uint32_t target_arch_largest_atomic_bits(ZigLLVM_ArchType arch) { case ZigLLVM_arm: case ZigLLVM_armeb: case ZigLLVM_hexagon: + case ZigLLVM_m68k: case ZigLLVM_le32: case ZigLLVM_mips: case ZigLLVM_mipsel: @@ -798,6 +802,8 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) { case ZigLLVM_aarch64_32: case ZigLLVM_riscv32: case ZigLLVM_riscv64: + case ZigLLVM_m68k: + case ZigLLVM_mips: case ZigLLVM_mipsel: case ZigLLVM_ppc: case ZigLLVM_ppcle: @@ -824,7 +830,6 @@ const char *arch_stack_pointer_register_name(ZigLLVM_ArchType arch) { case ZigLLVM_kalimba: case ZigLLVM_le32: case ZigLLVM_le64: - case ZigLLVM_mips: case ZigLLVM_mips64: case ZigLLVM_mips64el: case ZigLLVM_msp430: @@ -873,6 +878,7 @@ bool target_is_arm(const ZigTarget *target) { case ZigLLVM_bpfel: case ZigLLVM_csky: case ZigLLVM_hexagon: + case ZigLLVM_m68k: case ZigLLVM_lanai: case ZigLLVM_hsail: case ZigLLVM_hsail64: diff --git a/src/target.zig b/src/target.zig index 06483d68ff..0958f1d00f 100644 --- a/src/target.zig +++ b/src/target.zig @@ -34,6 +34,8 @@ pub const available_libcs = [_]ArchOsAbi{ .{ .arch = .i386, .os = .linux, .abi = .gnu }, .{ .arch = .i386, .os = .linux, .abi = .musl }, .{ .arch = .i386, .os = .windows, .abi = .gnu }, + .{ .arch = .m68k, .os = .linux, .abi = .gnu }, + .{ .arch = .m68k, .os = .linux, .abi = .musl }, .{ .arch = .mips64el, .os = .linux, .abi = .gnuabi64 }, .{ .arch = .mips64el, .os = .linux, .abi = .gnuabin32 }, .{ .arch = .mips64el, .os = .linux, .abi = .musl }, @@ -83,6 +85,7 @@ pub fn libCGenericName(target: std.Target) [:0]const u8 { .musl, .musleabi, .musleabihf, + .muslx32, .none, => return "musl", .code16, @@ -186,6 +189,7 @@ pub fn hasLlvmSupport(target: std.Target) bool { .bpfeb, .csky, .hexagon, + .m68k, .mips, .mipsel, .mips64, @@ -295,6 +299,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .bpfeb => .bpfeb, .csky => .csky, .hexagon => .hexagon, + .m68k => .m68k, .mips => .mips, .mipsel => .mipsel, .mips64 => .mips64, diff --git a/src/zig_clang.cpp b/src/zig_clang.cpp index 6611585f68..98d9259e0d 100644 --- a/src/zig_clang.cpp +++ b/src/zig_clang.cpp @@ -164,6 +164,10 @@ void ZigClang_detect_enum_CK(clang::CastKind x) { case clang::CK_DerivedToBase: case clang::CK_DerivedToBaseMemberPointer: case clang::CK_Dynamic: + case clang::CK_FixedPointCast: + case clang::CK_FixedPointToBoolean: + case clang::CK_FixedPointToFloating: + case clang::CK_FixedPointToIntegral: case clang::CK_FloatingCast: case clang::CK_FloatingComplexCast: case clang::CK_FloatingComplexToBoolean: @@ -171,6 +175,7 @@ void ZigClang_detect_enum_CK(clang::CastKind x) { case clang::CK_FloatingComplexToReal: case clang::CK_FloatingRealToComplex: case clang::CK_FloatingToBoolean: + case clang::CK_FloatingToFixedPoint: case clang::CK_FloatingToIntegral: case clang::CK_FunctionToPointerDecay: case clang::CK_IntToOCLSampler: @@ -181,13 +186,13 @@ void ZigClang_detect_enum_CK(clang::CastKind x) { case clang::CK_IntegralComplexToReal: case clang::CK_IntegralRealToComplex: case clang::CK_IntegralToBoolean: + case clang::CK_IntegralToFixedPoint: case clang::CK_IntegralToFloating: case clang::CK_IntegralToPointer: - case clang::CK_FloatingToFixedPoint: - case clang::CK_FixedPointToFloating: case clang::CK_LValueBitCast: - case clang::CK_LValueToRValueBitCast: case clang::CK_LValueToRValue: + case clang::CK_LValueToRValueBitCast: + case clang::CK_MatrixCast: case clang::CK_MemberPointerToBoolean: case clang::CK_NoOp: case clang::CK_NonAtomicToAtomic: @@ -203,10 +208,6 @@ void ZigClang_detect_enum_CK(clang::CastKind x) { case clang::CK_UserDefinedConversion: case clang::CK_VectorSplat: case clang::CK_ZeroToOCLOpaqueType: - case clang::CK_FixedPointCast: - case clang::CK_FixedPointToIntegral: - case clang::CK_IntegralToFixedPoint: - case clang::CK_FixedPointToBoolean: break; } }; @@ -236,6 +237,7 @@ static_assert((clang::CastKind)ZigClangCK_IntegralToPointer == clang::CK_Integra static_assert((clang::CastKind)ZigClangCK_PointerToIntegral == clang::CK_PointerToIntegral, ""); static_assert((clang::CastKind)ZigClangCK_PointerToBoolean == clang::CK_PointerToBoolean, ""); static_assert((clang::CastKind)ZigClangCK_ToVoid == clang::CK_ToVoid, ""); +static_assert((clang::CastKind)ZigClangCK_MatrixCast == clang::CK_MatrixCast, ""); static_assert((clang::CastKind)ZigClangCK_VectorSplat == clang::CK_VectorSplat, ""); static_assert((clang::CastKind)ZigClangCK_IntegralCast == clang::CK_IntegralCast, ""); static_assert((clang::CastKind)ZigClangCK_IntegralToBoolean == clang::CK_IntegralToBoolean, ""); @@ -411,13 +413,16 @@ void ZigClang_detect_enum_StmtClass(clang::Stmt::StmtClass x) { case ZigClangStmt_IndirectGotoStmtClass: case ZigClangStmt_MSDependentExistsStmtClass: case ZigClangStmt_NullStmtClass: + case ZigClangStmt_OMPCanonicalLoopClass: case ZigClangStmt_OMPAtomicDirectiveClass: case ZigClangStmt_OMPBarrierDirectiveClass: case ZigClangStmt_OMPCancelDirectiveClass: case ZigClangStmt_OMPCancellationPointDirectiveClass: case ZigClangStmt_OMPCriticalDirectiveClass: case ZigClangStmt_OMPDepobjDirectiveClass: + case ZigClangStmt_OMPDispatchDirectiveClass: case ZigClangStmt_OMPFlushDirectiveClass: + case ZigClangStmt_OMPInteropDirectiveClass: case ZigClangStmt_OMPDistributeDirectiveClass: case ZigClangStmt_OMPDistributeParallelForDirectiveClass: case ZigClangStmt_OMPDistributeParallelForSimdDirectiveClass: @@ -443,6 +448,9 @@ void ZigClang_detect_enum_StmtClass(clang::Stmt::StmtClass x) { case ZigClangStmt_OMPTeamsDistributeParallelForDirectiveClass: case ZigClangStmt_OMPTeamsDistributeParallelForSimdDirectiveClass: case ZigClangStmt_OMPTeamsDistributeSimdDirectiveClass: + case ZigClangStmt_OMPTileDirectiveClass: + case ZigClangStmt_OMPUnrollDirectiveClass: + case ZigClangStmt_OMPMaskedDirectiveClass: case ZigClangStmt_OMPMasterDirectiveClass: case ZigClangStmt_OMPOrderedDirectiveClass: case ZigClangStmt_OMPParallelDirectiveClass: @@ -591,6 +599,7 @@ void ZigClang_detect_enum_StmtClass(clang::Stmt::StmtClass x) { case ZigClangStmt_PseudoObjectExprClass: case ZigClangStmt_RecoveryExprClass: case ZigClangStmt_RequiresExprClass: + case ZigClangStmt_SYCLUniqueStableNameExprClass: case ZigClangStmt_ShuffleVectorExprClass: case ZigClangStmt_SizeOfPackExprClass: case ZigClangStmt_SourceLocExprClass: @@ -629,13 +638,16 @@ static_assert((clang::Stmt::StmtClass)ZigClangStmt_IfStmtClass == clang::Stmt::I static_assert((clang::Stmt::StmtClass)ZigClangStmt_IndirectGotoStmtClass == clang::Stmt::IndirectGotoStmtClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_MSDependentExistsStmtClass == clang::Stmt::MSDependentExistsStmtClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_NullStmtClass == clang::Stmt::NullStmtClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPCanonicalLoopClass == clang::Stmt::OMPCanonicalLoopClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPAtomicDirectiveClass == clang::Stmt::OMPAtomicDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPBarrierDirectiveClass == clang::Stmt::OMPBarrierDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPCancelDirectiveClass == clang::Stmt::OMPCancelDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPCancellationPointDirectiveClass == clang::Stmt::OMPCancellationPointDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPCriticalDirectiveClass == clang::Stmt::OMPCriticalDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPDepobjDirectiveClass == clang::Stmt::OMPDepobjDirectiveClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPDispatchDirectiveClass == clang::Stmt::OMPDispatchDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPFlushDirectiveClass == clang::Stmt::OMPFlushDirectiveClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPInteropDirectiveClass == clang::Stmt::OMPInteropDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPDistributeDirectiveClass == clang::Stmt::OMPDistributeDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPDistributeParallelForDirectiveClass == clang::Stmt::OMPDistributeParallelForDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPDistributeParallelForSimdDirectiveClass == clang::Stmt::OMPDistributeParallelForSimdDirectiveClass, ""); @@ -661,6 +673,9 @@ static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPTeamsDistributeDirectiveCl static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPTeamsDistributeParallelForDirectiveClass == clang::Stmt::OMPTeamsDistributeParallelForDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPTeamsDistributeParallelForSimdDirectiveClass == clang::Stmt::OMPTeamsDistributeParallelForSimdDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPTeamsDistributeSimdDirectiveClass == clang::Stmt::OMPTeamsDistributeSimdDirectiveClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPTileDirectiveClass == clang::Stmt::OMPTileDirectiveClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPUnrollDirectiveClass == clang::Stmt::OMPUnrollDirectiveClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPMaskedDirectiveClass == clang::Stmt::OMPMaskedDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPMasterDirectiveClass == clang::Stmt::OMPMasterDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPOrderedDirectiveClass == clang::Stmt::OMPOrderedDirectiveClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_OMPParallelDirectiveClass == clang::Stmt::OMPParallelDirectiveClass, ""); @@ -809,6 +824,7 @@ static_assert((clang::Stmt::StmtClass)ZigClangStmt_PredefinedExprClass == clang: static_assert((clang::Stmt::StmtClass)ZigClangStmt_PseudoObjectExprClass == clang::Stmt::PseudoObjectExprClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_RecoveryExprClass == clang::Stmt::RecoveryExprClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_RequiresExprClass == clang::Stmt::RequiresExprClass, ""); +static_assert((clang::Stmt::StmtClass)ZigClangStmt_SYCLUniqueStableNameExprClass == clang::Stmt::SYCLUniqueStableNameExprClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_ShuffleVectorExprClass == clang::Stmt::ShuffleVectorExprClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_SizeOfPackExprClass == clang::Stmt::SizeOfPackExprClass, ""); static_assert((clang::Stmt::StmtClass)ZigClangStmt_SourceLocExprClass == clang::Stmt::SourceLocExprClass, ""); @@ -876,6 +892,8 @@ void ZigClang_detect_enum_DeclKind(clang::Decl::Kind x) { case clang::Decl::Import: case clang::Decl::LifetimeExtendedTemporary: case clang::Decl::LinkageSpec: + case clang::Decl::Using: + case clang::Decl::UsingEnum: case clang::Decl::Label: case clang::Decl::Namespace: case clang::Decl::NamespaceAlias: @@ -904,7 +922,7 @@ void ZigClang_detect_enum_DeclKind(clang::Decl::Kind x) { case clang::Decl::TypeAlias: case clang::Decl::Typedef: case clang::Decl::UnresolvedUsingTypename: - case clang::Decl::Using: + case clang::Decl::UnresolvedUsingIfExists: case clang::Decl::UsingDirective: case clang::Decl::UsingPack: case clang::Decl::UsingShadow: @@ -961,6 +979,8 @@ static_assert((clang::Decl::Kind)ZigClangDeclFriendTemplate == clang::Decl::Frie static_assert((clang::Decl::Kind)ZigClangDeclImport == clang::Decl::Import, ""); static_assert((clang::Decl::Kind)ZigClangDeclLifetimeExtendedTemporary == clang::Decl::LifetimeExtendedTemporary, ""); static_assert((clang::Decl::Kind)ZigClangDeclLinkageSpec == clang::Decl::LinkageSpec, ""); +static_assert((clang::Decl::Kind)ZigClangDeclUsing == clang::Decl::Using, ""); +static_assert((clang::Decl::Kind)ZigClangDeclUsingEnum == clang::Decl::UsingEnum, ""); static_assert((clang::Decl::Kind)ZigClangDeclLabel == clang::Decl::Label, ""); static_assert((clang::Decl::Kind)ZigClangDeclNamespace == clang::Decl::Namespace, ""); static_assert((clang::Decl::Kind)ZigClangDeclNamespaceAlias == clang::Decl::NamespaceAlias, ""); @@ -989,8 +1009,8 @@ static_assert((clang::Decl::Kind)ZigClangDeclObjCTypeParam == clang::Decl::ObjCT static_assert((clang::Decl::Kind)ZigClangDeclTypeAlias == clang::Decl::TypeAlias, ""); static_assert((clang::Decl::Kind)ZigClangDeclTypedef == clang::Decl::Typedef, ""); static_assert((clang::Decl::Kind)ZigClangDeclUnresolvedUsingTypename == clang::Decl::UnresolvedUsingTypename, ""); +static_assert((clang::Decl::Kind)ZigClangDeclUnresolvedUsingIfExists == clang::Decl::UnresolvedUsingIfExists, ""); static_assert((clang::Decl::Kind)ZigClangDeclOMPAllocate == clang::Decl::OMPAllocate, ""); -static_assert((clang::Decl::Kind)ZigClangDeclUsing == clang::Decl::Using, ""); static_assert((clang::Decl::Kind)ZigClangDeclUsingDirective == clang::Decl::UsingDirective, ""); static_assert((clang::Decl::Kind)ZigClangDeclUsingPack == clang::Decl::UsingPack, ""); static_assert((clang::Decl::Kind)ZigClangDeclUsingShadow == clang::Decl::UsingShadow, ""); @@ -1032,177 +1052,243 @@ static_assert((clang::Decl::Kind)ZigClangDeclTranslationUnit == clang::Decl::Tra void ZigClang_detect_enum_BuiltinTypeKind(clang::BuiltinType::Kind x) { switch (x) { - case clang::BuiltinType::OCLImage1dRO: - case clang::BuiltinType::OCLImage1dArrayRO: - case clang::BuiltinType::OCLImage1dBufferRO: - case clang::BuiltinType::OCLImage2dRO: - case clang::BuiltinType::OCLImage2dArrayRO: - case clang::BuiltinType::OCLImage2dDepthRO: - case clang::BuiltinType::OCLImage2dArrayDepthRO: - case clang::BuiltinType::OCLImage2dMSAARO: - case clang::BuiltinType::OCLImage2dArrayMSAARO: - case clang::BuiltinType::OCLImage2dMSAADepthRO: - case clang::BuiltinType::OCLImage2dArrayMSAADepthRO: - case clang::BuiltinType::OCLImage3dRO: - case clang::BuiltinType::OCLImage1dWO: - case clang::BuiltinType::OCLImage1dArrayWO: - case clang::BuiltinType::OCLImage1dBufferWO: - case clang::BuiltinType::OCLImage2dWO: - case clang::BuiltinType::OCLImage2dArrayWO: - case clang::BuiltinType::OCLImage2dDepthWO: - case clang::BuiltinType::OCLImage2dArrayDepthWO: - case clang::BuiltinType::OCLImage2dMSAAWO: - case clang::BuiltinType::OCLImage2dArrayMSAAWO: - case clang::BuiltinType::OCLImage2dMSAADepthWO: - case clang::BuiltinType::OCLImage2dArrayMSAADepthWO: - case clang::BuiltinType::OCLImage3dWO: - case clang::BuiltinType::OCLImage1dRW: - case clang::BuiltinType::OCLImage1dArrayRW: - case clang::BuiltinType::OCLImage1dBufferRW: - case clang::BuiltinType::OCLImage2dRW: - case clang::BuiltinType::OCLImage2dArrayRW: - case clang::BuiltinType::OCLImage2dDepthRW: - case clang::BuiltinType::OCLImage2dArrayDepthRW: - case clang::BuiltinType::OCLImage2dMSAARW: - case clang::BuiltinType::OCLImage2dArrayMSAARW: - case clang::BuiltinType::OCLImage2dMSAADepthRW: - case clang::BuiltinType::OCLImage2dArrayMSAADepthRW: - case clang::BuiltinType::OCLImage3dRW: - case clang::BuiltinType::OCLIntelSubgroupAVCMcePayload: - case clang::BuiltinType::OCLIntelSubgroupAVCImePayload: - case clang::BuiltinType::OCLIntelSubgroupAVCRefPayload: - case clang::BuiltinType::OCLIntelSubgroupAVCSicPayload: - case clang::BuiltinType::OCLIntelSubgroupAVCMceResult: - case clang::BuiltinType::OCLIntelSubgroupAVCImeResult: - case clang::BuiltinType::OCLIntelSubgroupAVCRefResult: - case clang::BuiltinType::OCLIntelSubgroupAVCSicResult: - case clang::BuiltinType::OCLIntelSubgroupAVCImeResultSingleRefStreamout: - case clang::BuiltinType::OCLIntelSubgroupAVCImeResultDualRefStreamout: - case clang::BuiltinType::OCLIntelSubgroupAVCImeSingleRefStreamin: - case clang::BuiltinType::OCLIntelSubgroupAVCImeDualRefStreamin: - case clang::BuiltinType::SveInt8: - case clang::BuiltinType::SveInt16: - case clang::BuiltinType::SveInt32: - case clang::BuiltinType::SveInt64: - case clang::BuiltinType::SveUint8: - case clang::BuiltinType::SveUint16: - case clang::BuiltinType::SveUint32: - case clang::BuiltinType::SveUint64: - case clang::BuiltinType::SveFloat16: - case clang::BuiltinType::SveFloat32: - case clang::BuiltinType::SveFloat64: - case clang::BuiltinType::SveBFloat16: - case clang::BuiltinType::SveInt8x2: - case clang::BuiltinType::SveInt16x2: - case clang::BuiltinType::SveInt32x2: - case clang::BuiltinType::SveInt64x2: - case clang::BuiltinType::SveUint8x2: - case clang::BuiltinType::SveUint16x2: - case clang::BuiltinType::SveUint32x2: - case clang::BuiltinType::SveUint64x2: - case clang::BuiltinType::SveFloat16x2: - case clang::BuiltinType::SveFloat32x2: - case clang::BuiltinType::SveFloat64x2: - case clang::BuiltinType::SveBFloat16x2: - case clang::BuiltinType::SveInt8x3: - case clang::BuiltinType::SveInt16x3: - case clang::BuiltinType::SveInt32x3: - case clang::BuiltinType::SveInt64x3: - case clang::BuiltinType::SveUint8x3: - case clang::BuiltinType::SveUint16x3: - case clang::BuiltinType::SveUint32x3: - case clang::BuiltinType::SveUint64x3: - case clang::BuiltinType::SveFloat16x3: - case clang::BuiltinType::SveFloat32x3: - case clang::BuiltinType::SveFloat64x3: - case clang::BuiltinType::SveBFloat16x3: - case clang::BuiltinType::SveInt8x4: - case clang::BuiltinType::SveInt16x4: - case clang::BuiltinType::SveInt32x4: - case clang::BuiltinType::SveInt64x4: - case clang::BuiltinType::SveUint8x4: - case clang::BuiltinType::SveUint16x4: - case clang::BuiltinType::SveUint32x4: - case clang::BuiltinType::SveUint64x4: - case clang::BuiltinType::SveFloat16x4: - case clang::BuiltinType::SveFloat32x4: - case clang::BuiltinType::SveFloat64x4: - case clang::BuiltinType::SveBFloat16x4: - case clang::BuiltinType::SveBool: - case clang::BuiltinType::VectorQuad: - case clang::BuiltinType::VectorPair: - case clang::BuiltinType::Void: - case clang::BuiltinType::Bool: - case clang::BuiltinType::Char_U: - case clang::BuiltinType::UChar: - case clang::BuiltinType::WChar_U: - case clang::BuiltinType::Char8: - case clang::BuiltinType::Char16: - case clang::BuiltinType::Char32: - case clang::BuiltinType::UShort: - case clang::BuiltinType::UInt: - case clang::BuiltinType::ULong: - case clang::BuiltinType::ULongLong: - case clang::BuiltinType::UInt128: - case clang::BuiltinType::Char_S: - case clang::BuiltinType::SChar: - case clang::BuiltinType::WChar_S: - case clang::BuiltinType::Short: - case clang::BuiltinType::Int: - case clang::BuiltinType::Long: - case clang::BuiltinType::LongLong: - case clang::BuiltinType::Int128: - case clang::BuiltinType::ShortAccum: - case clang::BuiltinType::Accum: - case clang::BuiltinType::LongAccum: - case clang::BuiltinType::UShortAccum: - case clang::BuiltinType::UAccum: - case clang::BuiltinType::ULongAccum: - case clang::BuiltinType::ShortFract: - case clang::BuiltinType::Fract: - case clang::BuiltinType::LongFract: - case clang::BuiltinType::UShortFract: - case clang::BuiltinType::UFract: - case clang::BuiltinType::ULongFract: - case clang::BuiltinType::SatShortAccum: - case clang::BuiltinType::SatAccum: - case clang::BuiltinType::SatLongAccum: - case clang::BuiltinType::SatUShortAccum: - case clang::BuiltinType::SatUAccum: - case clang::BuiltinType::SatULongAccum: - case clang::BuiltinType::SatShortFract: - case clang::BuiltinType::SatFract: - case clang::BuiltinType::SatLongFract: - case clang::BuiltinType::SatUShortFract: - case clang::BuiltinType::SatUFract: - case clang::BuiltinType::SatULongFract: - case clang::BuiltinType::Half: - case clang::BuiltinType::Float: - case clang::BuiltinType::Double: - case clang::BuiltinType::LongDouble: - case clang::BuiltinType::Float16: - case clang::BuiltinType::BFloat16: - case clang::BuiltinType::Float128: - case clang::BuiltinType::NullPtr: - case clang::BuiltinType::ObjCId: - case clang::BuiltinType::ObjCClass: - case clang::BuiltinType::ObjCSel: - case clang::BuiltinType::OCLSampler: - case clang::BuiltinType::OCLEvent: - case clang::BuiltinType::OCLClkEvent: - case clang::BuiltinType::OCLQueue: - case clang::BuiltinType::OCLReserveID: - case clang::BuiltinType::Dependent: - case clang::BuiltinType::Overload: - case clang::BuiltinType::BoundMember: - case clang::BuiltinType::PseudoObject: - case clang::BuiltinType::UnknownAny: - case clang::BuiltinType::BuiltinFn: - case clang::BuiltinType::ARCUnbridgedCast: - case clang::BuiltinType::IncompleteMatrixIdx: - case clang::BuiltinType::OMPArraySection: - case clang::BuiltinType::OMPArrayShaping: - case clang::BuiltinType::OMPIterator: + case ZigClangBuiltinTypeOCLImage1dRO: + case ZigClangBuiltinTypeOCLImage1dArrayRO: + case ZigClangBuiltinTypeOCLImage1dBufferRO: + case ZigClangBuiltinTypeOCLImage2dRO: + case ZigClangBuiltinTypeOCLImage2dArrayRO: + case ZigClangBuiltinTypeOCLImage2dDepthRO: + case ZigClangBuiltinTypeOCLImage2dArrayDepthRO: + case ZigClangBuiltinTypeOCLImage2dMSAARO: + case ZigClangBuiltinTypeOCLImage2dArrayMSAARO: + case ZigClangBuiltinTypeOCLImage2dMSAADepthRO: + case ZigClangBuiltinTypeOCLImage2dArrayMSAADepthRO: + case ZigClangBuiltinTypeOCLImage3dRO: + case ZigClangBuiltinTypeOCLImage1dWO: + case ZigClangBuiltinTypeOCLImage1dArrayWO: + case ZigClangBuiltinTypeOCLImage1dBufferWO: + case ZigClangBuiltinTypeOCLImage2dWO: + case ZigClangBuiltinTypeOCLImage2dArrayWO: + case ZigClangBuiltinTypeOCLImage2dDepthWO: + case ZigClangBuiltinTypeOCLImage2dArrayDepthWO: + case ZigClangBuiltinTypeOCLImage2dMSAAWO: + case ZigClangBuiltinTypeOCLImage2dArrayMSAAWO: + case ZigClangBuiltinTypeOCLImage2dMSAADepthWO: + case ZigClangBuiltinTypeOCLImage2dArrayMSAADepthWO: + case ZigClangBuiltinTypeOCLImage3dWO: + case ZigClangBuiltinTypeOCLImage1dRW: + case ZigClangBuiltinTypeOCLImage1dArrayRW: + case ZigClangBuiltinTypeOCLImage1dBufferRW: + case ZigClangBuiltinTypeOCLImage2dRW: + case ZigClangBuiltinTypeOCLImage2dArrayRW: + case ZigClangBuiltinTypeOCLImage2dDepthRW: + case ZigClangBuiltinTypeOCLImage2dArrayDepthRW: + case ZigClangBuiltinTypeOCLImage2dMSAARW: + case ZigClangBuiltinTypeOCLImage2dArrayMSAARW: + case ZigClangBuiltinTypeOCLImage2dMSAADepthRW: + case ZigClangBuiltinTypeOCLImage2dArrayMSAADepthRW: + case ZigClangBuiltinTypeOCLImage3dRW: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCMcePayload: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCImePayload: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCRefPayload: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCSicPayload: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCMceResult: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCImeResult: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCRefResult: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCSicResult: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCImeResultSingleRefStreamout: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCImeResultDualRefStreamout: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCImeSingleRefStreamin: + case ZigClangBuiltinTypeOCLIntelSubgroupAVCImeDualRefStreamin: + case ZigClangBuiltinTypeSveInt8: + case ZigClangBuiltinTypeSveInt16: + case ZigClangBuiltinTypeSveInt32: + case ZigClangBuiltinTypeSveInt64: + case ZigClangBuiltinTypeSveUint8: + case ZigClangBuiltinTypeSveUint16: + case ZigClangBuiltinTypeSveUint32: + case ZigClangBuiltinTypeSveUint64: + case ZigClangBuiltinTypeSveFloat16: + case ZigClangBuiltinTypeSveFloat32: + case ZigClangBuiltinTypeSveFloat64: + case ZigClangBuiltinTypeSveBFloat16: + case ZigClangBuiltinTypeSveInt8x2: + case ZigClangBuiltinTypeSveInt16x2: + case ZigClangBuiltinTypeSveInt32x2: + case ZigClangBuiltinTypeSveInt64x2: + case ZigClangBuiltinTypeSveUint8x2: + case ZigClangBuiltinTypeSveUint16x2: + case ZigClangBuiltinTypeSveUint32x2: + case ZigClangBuiltinTypeSveUint64x2: + case ZigClangBuiltinTypeSveFloat16x2: + case ZigClangBuiltinTypeSveFloat32x2: + case ZigClangBuiltinTypeSveFloat64x2: + case ZigClangBuiltinTypeSveBFloat16x2: + case ZigClangBuiltinTypeSveInt8x3: + case ZigClangBuiltinTypeSveInt16x3: + case ZigClangBuiltinTypeSveInt32x3: + case ZigClangBuiltinTypeSveInt64x3: + case ZigClangBuiltinTypeSveUint8x3: + case ZigClangBuiltinTypeSveUint16x3: + case ZigClangBuiltinTypeSveUint32x3: + case ZigClangBuiltinTypeSveUint64x3: + case ZigClangBuiltinTypeSveFloat16x3: + case ZigClangBuiltinTypeSveFloat32x3: + case ZigClangBuiltinTypeSveFloat64x3: + case ZigClangBuiltinTypeSveBFloat16x3: + case ZigClangBuiltinTypeSveInt8x4: + case ZigClangBuiltinTypeSveInt16x4: + case ZigClangBuiltinTypeSveInt32x4: + case ZigClangBuiltinTypeSveInt64x4: + case ZigClangBuiltinTypeSveUint8x4: + case ZigClangBuiltinTypeSveUint16x4: + case ZigClangBuiltinTypeSveUint32x4: + case ZigClangBuiltinTypeSveUint64x4: + case ZigClangBuiltinTypeSveFloat16x4: + case ZigClangBuiltinTypeSveFloat32x4: + case ZigClangBuiltinTypeSveFloat64x4: + case ZigClangBuiltinTypeSveBFloat16x4: + case ZigClangBuiltinTypeSveBool: + case ZigClangBuiltinTypeVectorQuad: + case ZigClangBuiltinTypeVectorPair: + case ZigClangBuiltinTypeRvvInt8mf8: + case ZigClangBuiltinTypeRvvInt8mf4: + case ZigClangBuiltinTypeRvvInt8mf2: + case ZigClangBuiltinTypeRvvInt8m1: + case ZigClangBuiltinTypeRvvInt8m2: + case ZigClangBuiltinTypeRvvInt8m4: + case ZigClangBuiltinTypeRvvInt8m8: + case ZigClangBuiltinTypeRvvUint8mf8: + case ZigClangBuiltinTypeRvvUint8mf4: + case ZigClangBuiltinTypeRvvUint8mf2: + case ZigClangBuiltinTypeRvvUint8m1: + case ZigClangBuiltinTypeRvvUint8m2: + case ZigClangBuiltinTypeRvvUint8m4: + case ZigClangBuiltinTypeRvvUint8m8: + case ZigClangBuiltinTypeRvvInt16mf4: + case ZigClangBuiltinTypeRvvInt16mf2: + case ZigClangBuiltinTypeRvvInt16m1: + case ZigClangBuiltinTypeRvvInt16m2: + case ZigClangBuiltinTypeRvvInt16m4: + case ZigClangBuiltinTypeRvvInt16m8: + case ZigClangBuiltinTypeRvvUint16mf4: + case ZigClangBuiltinTypeRvvUint16mf2: + case ZigClangBuiltinTypeRvvUint16m1: + case ZigClangBuiltinTypeRvvUint16m2: + case ZigClangBuiltinTypeRvvUint16m4: + case ZigClangBuiltinTypeRvvUint16m8: + case ZigClangBuiltinTypeRvvInt32mf2: + case ZigClangBuiltinTypeRvvInt32m1: + case ZigClangBuiltinTypeRvvInt32m2: + case ZigClangBuiltinTypeRvvInt32m4: + case ZigClangBuiltinTypeRvvInt32m8: + case ZigClangBuiltinTypeRvvUint32mf2: + case ZigClangBuiltinTypeRvvUint32m1: + case ZigClangBuiltinTypeRvvUint32m2: + case ZigClangBuiltinTypeRvvUint32m4: + case ZigClangBuiltinTypeRvvUint32m8: + case ZigClangBuiltinTypeRvvInt64m1: + case ZigClangBuiltinTypeRvvInt64m2: + case ZigClangBuiltinTypeRvvInt64m4: + case ZigClangBuiltinTypeRvvInt64m8: + case ZigClangBuiltinTypeRvvUint64m1: + case ZigClangBuiltinTypeRvvUint64m2: + case ZigClangBuiltinTypeRvvUint64m4: + case ZigClangBuiltinTypeRvvUint64m8: + case ZigClangBuiltinTypeRvvFloat16mf4: + case ZigClangBuiltinTypeRvvFloat16mf2: + case ZigClangBuiltinTypeRvvFloat16m1: + case ZigClangBuiltinTypeRvvFloat16m2: + case ZigClangBuiltinTypeRvvFloat16m4: + case ZigClangBuiltinTypeRvvFloat16m8: + case ZigClangBuiltinTypeRvvFloat32mf2: + case ZigClangBuiltinTypeRvvFloat32m1: + case ZigClangBuiltinTypeRvvFloat32m2: + case ZigClangBuiltinTypeRvvFloat32m4: + case ZigClangBuiltinTypeRvvFloat32m8: + case ZigClangBuiltinTypeRvvFloat64m1: + case ZigClangBuiltinTypeRvvFloat64m2: + case ZigClangBuiltinTypeRvvFloat64m4: + case ZigClangBuiltinTypeRvvFloat64m8: + case ZigClangBuiltinTypeRvvBool1: + case ZigClangBuiltinTypeRvvBool2: + case ZigClangBuiltinTypeRvvBool4: + case ZigClangBuiltinTypeRvvBool8: + case ZigClangBuiltinTypeRvvBool16: + case ZigClangBuiltinTypeRvvBool32: + case ZigClangBuiltinTypeRvvBool64: + case ZigClangBuiltinTypeVoid: + case ZigClangBuiltinTypeBool: + case ZigClangBuiltinTypeChar_U: + case ZigClangBuiltinTypeUChar: + case ZigClangBuiltinTypeWChar_U: + case ZigClangBuiltinTypeChar8: + case ZigClangBuiltinTypeChar16: + case ZigClangBuiltinTypeChar32: + case ZigClangBuiltinTypeUShort: + case ZigClangBuiltinTypeUInt: + case ZigClangBuiltinTypeULong: + case ZigClangBuiltinTypeULongLong: + case ZigClangBuiltinTypeUInt128: + case ZigClangBuiltinTypeChar_S: + case ZigClangBuiltinTypeSChar: + case ZigClangBuiltinTypeWChar_S: + case ZigClangBuiltinTypeShort: + case ZigClangBuiltinTypeInt: + case ZigClangBuiltinTypeLong: + case ZigClangBuiltinTypeLongLong: + case ZigClangBuiltinTypeInt128: + case ZigClangBuiltinTypeShortAccum: + case ZigClangBuiltinTypeAccum: + case ZigClangBuiltinTypeLongAccum: + case ZigClangBuiltinTypeUShortAccum: + case ZigClangBuiltinTypeUAccum: + case ZigClangBuiltinTypeULongAccum: + case ZigClangBuiltinTypeShortFract: + case ZigClangBuiltinTypeFract: + case ZigClangBuiltinTypeLongFract: + case ZigClangBuiltinTypeUShortFract: + case ZigClangBuiltinTypeUFract: + case ZigClangBuiltinTypeULongFract: + case ZigClangBuiltinTypeSatShortAccum: + case ZigClangBuiltinTypeSatAccum: + case ZigClangBuiltinTypeSatLongAccum: + case ZigClangBuiltinTypeSatUShortAccum: + case ZigClangBuiltinTypeSatUAccum: + case ZigClangBuiltinTypeSatULongAccum: + case ZigClangBuiltinTypeSatShortFract: + case ZigClangBuiltinTypeSatFract: + case ZigClangBuiltinTypeSatLongFract: + case ZigClangBuiltinTypeSatUShortFract: + case ZigClangBuiltinTypeSatUFract: + case ZigClangBuiltinTypeSatULongFract: + case ZigClangBuiltinTypeHalf: + case ZigClangBuiltinTypeFloat: + case ZigClangBuiltinTypeDouble: + case ZigClangBuiltinTypeLongDouble: + case ZigClangBuiltinTypeFloat16: + case ZigClangBuiltinTypeBFloat16: + case ZigClangBuiltinTypeFloat128: + case ZigClangBuiltinTypeNullPtr: + case ZigClangBuiltinTypeObjCId: + case ZigClangBuiltinTypeObjCClass: + case ZigClangBuiltinTypeObjCSel: + case ZigClangBuiltinTypeOCLSampler: + case ZigClangBuiltinTypeOCLEvent: + case ZigClangBuiltinTypeOCLClkEvent: + case ZigClangBuiltinTypeOCLQueue: + case ZigClangBuiltinTypeOCLReserveID: + case ZigClangBuiltinTypeDependent: + case ZigClangBuiltinTypeOverload: + case ZigClangBuiltinTypeBoundMember: + case ZigClangBuiltinTypePseudoObject: + case ZigClangBuiltinTypeUnknownAny: + case ZigClangBuiltinTypeBuiltinFn: + case ZigClangBuiltinTypeARCUnbridgedCast: + case ZigClangBuiltinTypeIncompleteMatrixIdx: + case ZigClangBuiltinTypeOMPArraySection: + case ZigClangBuiltinTypeOMPArrayShaping: + case ZigClangBuiltinTypeOMPIterator: break; } } @@ -1306,6 +1392,72 @@ static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeSveBFloat16x4 == clan static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeSveBool == clang::BuiltinType::SveBool, ""); static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeVectorQuad == clang::BuiltinType::VectorQuad, ""); static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeVectorPair == clang::BuiltinType::VectorPair, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8mf8 == clang::BuiltinType::RvvInt8mf8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8mf4 == clang::BuiltinType::RvvInt8mf4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8mf2 == clang::BuiltinType::RvvInt8mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8m1 == clang::BuiltinType::RvvInt8m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8m2 == clang::BuiltinType::RvvInt8m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8m4 == clang::BuiltinType::RvvInt8m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt8m8 == clang::BuiltinType::RvvInt8m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8mf8 == clang::BuiltinType::RvvUint8mf8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8mf4 == clang::BuiltinType::RvvUint8mf4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8mf2 == clang::BuiltinType::RvvUint8mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8m1 == clang::BuiltinType::RvvUint8m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8m2 == clang::BuiltinType::RvvUint8m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8m4 == clang::BuiltinType::RvvUint8m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint8m8 == clang::BuiltinType::RvvUint8m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt16mf4 == clang::BuiltinType::RvvInt16mf4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt16mf2 == clang::BuiltinType::RvvInt16mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt16m1 == clang::BuiltinType::RvvInt16m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt16m2 == clang::BuiltinType::RvvInt16m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt16m4 == clang::BuiltinType::RvvInt16m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt16m8 == clang::BuiltinType::RvvInt16m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint16mf4 == clang::BuiltinType::RvvUint16mf4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint16mf2 == clang::BuiltinType::RvvUint16mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint16m1 == clang::BuiltinType::RvvUint16m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint16m2 == clang::BuiltinType::RvvUint16m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint16m4 == clang::BuiltinType::RvvUint16m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint16m8 == clang::BuiltinType::RvvUint16m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt32mf2 == clang::BuiltinType::RvvInt32mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt32m1 == clang::BuiltinType::RvvInt32m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt32m2 == clang::BuiltinType::RvvInt32m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt32m4 == clang::BuiltinType::RvvInt32m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt32m8 == clang::BuiltinType::RvvInt32m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint32mf2 == clang::BuiltinType::RvvUint32mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint32m1 == clang::BuiltinType::RvvUint32m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint32m2 == clang::BuiltinType::RvvUint32m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint32m4 == clang::BuiltinType::RvvUint32m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint32m8 == clang::BuiltinType::RvvUint32m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt64m1 == clang::BuiltinType::RvvInt64m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt64m2 == clang::BuiltinType::RvvInt64m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt64m4 == clang::BuiltinType::RvvInt64m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvInt64m8 == clang::BuiltinType::RvvInt64m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint64m1 == clang::BuiltinType::RvvUint64m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint64m2 == clang::BuiltinType::RvvUint64m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint64m4 == clang::BuiltinType::RvvUint64m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvUint64m8 == clang::BuiltinType::RvvUint64m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat16mf4 == clang::BuiltinType::RvvFloat16mf4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat16mf2 == clang::BuiltinType::RvvFloat16mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat16m1 == clang::BuiltinType::RvvFloat16m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat16m2 == clang::BuiltinType::RvvFloat16m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat16m4 == clang::BuiltinType::RvvFloat16m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat16m8 == clang::BuiltinType::RvvFloat16m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat32mf2 == clang::BuiltinType::RvvFloat32mf2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat32m1 == clang::BuiltinType::RvvFloat32m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat32m2 == clang::BuiltinType::RvvFloat32m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat32m4 == clang::BuiltinType::RvvFloat32m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat32m8 == clang::BuiltinType::RvvFloat32m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat64m1 == clang::BuiltinType::RvvFloat64m1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat64m2 == clang::BuiltinType::RvvFloat64m2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat64m4 == clang::BuiltinType::RvvFloat64m4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvFloat64m8 == clang::BuiltinType::RvvFloat64m8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool1 == clang::BuiltinType::RvvBool1, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool2 == clang::BuiltinType::RvvBool2, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool4 == clang::BuiltinType::RvvBool4, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool8 == clang::BuiltinType::RvvBool8, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool16 == clang::BuiltinType::RvvBool16, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool32 == clang::BuiltinType::RvvBool32, ""); +static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeRvvBool64 == clang::BuiltinType::RvvBool64, ""); static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeVoid == clang::BuiltinType::Void, ""); static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeBool == clang::BuiltinType::Bool, ""); static_assert((clang::BuiltinType::Kind)ZigClangBuiltinTypeChar_U == clang::BuiltinType::Char_U, ""); @@ -1396,6 +1548,7 @@ void ZigClang_detect_enum_CallingConv(clang::CallingConv x) { case clang::CC_SpirFunction: case clang::CC_OpenCLKernel: case clang::CC_Swift: + case clang::CC_SwiftAsync: case clang::CC_PreserveMost: case clang::CC_PreserveAll: case clang::CC_AArch64VectorCall: @@ -1418,6 +1571,7 @@ static_assert((clang::CallingConv)ZigClangCallingConv_IntelOclBicc == clang::CC_ static_assert((clang::CallingConv)ZigClangCallingConv_SpirFunction == clang::CC_SpirFunction, ""); static_assert((clang::CallingConv)ZigClangCallingConv_OpenCLKernel == clang::CC_OpenCLKernel, ""); static_assert((clang::CallingConv)ZigClangCallingConv_Swift == clang::CC_Swift, ""); +static_assert((clang::CallingConv)ZigClangCallingConv_SwiftAsync == clang::CC_SwiftAsync, ""); static_assert((clang::CallingConv)ZigClangCallingConv_PreserveMost == clang::CC_PreserveMost, ""); static_assert((clang::CallingConv)ZigClangCallingConv_PreserveAll == clang::CC_PreserveAll, ""); static_assert((clang::CallingConv)ZigClangCallingConv_AArch64VectorCall == clang::CC_AArch64VectorCall, ""); diff --git a/src/zig_clang.h b/src/zig_clang.h index 0e7a8b2990..19fe81be91 100644 --- a/src/zig_clang.h +++ b/src/zig_clang.h @@ -318,13 +318,16 @@ enum ZigClangStmtClass { ZigClangStmt_IndirectGotoStmtClass, ZigClangStmt_MSDependentExistsStmtClass, ZigClangStmt_NullStmtClass, + ZigClangStmt_OMPCanonicalLoopClass, ZigClangStmt_OMPAtomicDirectiveClass, ZigClangStmt_OMPBarrierDirectiveClass, ZigClangStmt_OMPCancelDirectiveClass, ZigClangStmt_OMPCancellationPointDirectiveClass, ZigClangStmt_OMPCriticalDirectiveClass, ZigClangStmt_OMPDepobjDirectiveClass, + ZigClangStmt_OMPDispatchDirectiveClass, ZigClangStmt_OMPFlushDirectiveClass, + ZigClangStmt_OMPInteropDirectiveClass, ZigClangStmt_OMPDistributeDirectiveClass, ZigClangStmt_OMPDistributeParallelForDirectiveClass, ZigClangStmt_OMPDistributeParallelForSimdDirectiveClass, @@ -350,6 +353,9 @@ enum ZigClangStmtClass { ZigClangStmt_OMPTeamsDistributeParallelForDirectiveClass, ZigClangStmt_OMPTeamsDistributeParallelForSimdDirectiveClass, ZigClangStmt_OMPTeamsDistributeSimdDirectiveClass, + ZigClangStmt_OMPTileDirectiveClass, + ZigClangStmt_OMPUnrollDirectiveClass, + ZigClangStmt_OMPMaskedDirectiveClass, ZigClangStmt_OMPMasterDirectiveClass, ZigClangStmt_OMPOrderedDirectiveClass, ZigClangStmt_OMPParallelDirectiveClass, @@ -498,6 +504,7 @@ enum ZigClangStmtClass { ZigClangStmt_PseudoObjectExprClass, ZigClangStmt_RecoveryExprClass, ZigClangStmt_RequiresExprClass, + ZigClangStmt_SYCLUniqueStableNameExprClass, ZigClangStmt_ShuffleVectorExprClass, ZigClangStmt_SizeOfPackExprClass, ZigClangStmt_SourceLocExprClass, @@ -540,6 +547,7 @@ enum ZigClangCK { ZigClangCK_PointerToIntegral, ZigClangCK_PointerToBoolean, ZigClangCK_ToVoid, + ZigClangCK_MatrixCast, ZigClangCK_VectorSplat, ZigClangCK_IntegralCast, ZigClangCK_IntegralToBoolean, @@ -595,6 +603,8 @@ enum ZigClangDeclKind { ZigClangDeclImport, ZigClangDeclLifetimeExtendedTemporary, ZigClangDeclLinkageSpec, + ZigClangDeclUsing, + ZigClangDeclUsingEnum, ZigClangDeclLabel, ZigClangDeclNamespace, ZigClangDeclNamespaceAlias, @@ -623,7 +633,7 @@ enum ZigClangDeclKind { ZigClangDeclTypeAlias, ZigClangDeclTypedef, ZigClangDeclUnresolvedUsingTypename, - ZigClangDeclUsing, + ZigClangDeclUnresolvedUsingIfExists, ZigClangDeclUsingDirective, ZigClangDeclUsingPack, ZigClangDeclUsingShadow, @@ -765,6 +775,72 @@ enum ZigClangBuiltinTypeKind { ZigClangBuiltinTypeSveBool, ZigClangBuiltinTypeVectorQuad, ZigClangBuiltinTypeVectorPair, + ZigClangBuiltinTypeRvvInt8mf8, + ZigClangBuiltinTypeRvvInt8mf4, + ZigClangBuiltinTypeRvvInt8mf2, + ZigClangBuiltinTypeRvvInt8m1, + ZigClangBuiltinTypeRvvInt8m2, + ZigClangBuiltinTypeRvvInt8m4, + ZigClangBuiltinTypeRvvInt8m8, + ZigClangBuiltinTypeRvvUint8mf8, + ZigClangBuiltinTypeRvvUint8mf4, + ZigClangBuiltinTypeRvvUint8mf2, + ZigClangBuiltinTypeRvvUint8m1, + ZigClangBuiltinTypeRvvUint8m2, + ZigClangBuiltinTypeRvvUint8m4, + ZigClangBuiltinTypeRvvUint8m8, + ZigClangBuiltinTypeRvvInt16mf4, + ZigClangBuiltinTypeRvvInt16mf2, + ZigClangBuiltinTypeRvvInt16m1, + ZigClangBuiltinTypeRvvInt16m2, + ZigClangBuiltinTypeRvvInt16m4, + ZigClangBuiltinTypeRvvInt16m8, + ZigClangBuiltinTypeRvvUint16mf4, + ZigClangBuiltinTypeRvvUint16mf2, + ZigClangBuiltinTypeRvvUint16m1, + ZigClangBuiltinTypeRvvUint16m2, + ZigClangBuiltinTypeRvvUint16m4, + ZigClangBuiltinTypeRvvUint16m8, + ZigClangBuiltinTypeRvvInt32mf2, + ZigClangBuiltinTypeRvvInt32m1, + ZigClangBuiltinTypeRvvInt32m2, + ZigClangBuiltinTypeRvvInt32m4, + ZigClangBuiltinTypeRvvInt32m8, + ZigClangBuiltinTypeRvvUint32mf2, + ZigClangBuiltinTypeRvvUint32m1, + ZigClangBuiltinTypeRvvUint32m2, + ZigClangBuiltinTypeRvvUint32m4, + ZigClangBuiltinTypeRvvUint32m8, + ZigClangBuiltinTypeRvvInt64m1, + ZigClangBuiltinTypeRvvInt64m2, + ZigClangBuiltinTypeRvvInt64m4, + ZigClangBuiltinTypeRvvInt64m8, + ZigClangBuiltinTypeRvvUint64m1, + ZigClangBuiltinTypeRvvUint64m2, + ZigClangBuiltinTypeRvvUint64m4, + ZigClangBuiltinTypeRvvUint64m8, + ZigClangBuiltinTypeRvvFloat16mf4, + ZigClangBuiltinTypeRvvFloat16mf2, + ZigClangBuiltinTypeRvvFloat16m1, + ZigClangBuiltinTypeRvvFloat16m2, + ZigClangBuiltinTypeRvvFloat16m4, + ZigClangBuiltinTypeRvvFloat16m8, + ZigClangBuiltinTypeRvvFloat32mf2, + ZigClangBuiltinTypeRvvFloat32m1, + ZigClangBuiltinTypeRvvFloat32m2, + ZigClangBuiltinTypeRvvFloat32m4, + ZigClangBuiltinTypeRvvFloat32m8, + ZigClangBuiltinTypeRvvFloat64m1, + ZigClangBuiltinTypeRvvFloat64m2, + ZigClangBuiltinTypeRvvFloat64m4, + ZigClangBuiltinTypeRvvFloat64m8, + ZigClangBuiltinTypeRvvBool1, + ZigClangBuiltinTypeRvvBool2, + ZigClangBuiltinTypeRvvBool4, + ZigClangBuiltinTypeRvvBool8, + ZigClangBuiltinTypeRvvBool16, + ZigClangBuiltinTypeRvvBool32, + ZigClangBuiltinTypeRvvBool64, ZigClangBuiltinTypeVoid, ZigClangBuiltinTypeBool, ZigClangBuiltinTypeChar_U, @@ -855,6 +931,7 @@ enum ZigClangCallingConv { ZigClangCallingConv_SpirFunction, // default for OpenCL functions on SPIR target ZigClangCallingConv_OpenCLKernel, // inferred for OpenCL kernels ZigClangCallingConv_Swift, // __attribute__((swiftcall)) + ZigClangCallingConv_SwiftAsync, // __attribute__((swiftasynccall)) ZigClangCallingConv_PreserveMost, // __attribute__((preserve_most)) ZigClangCallingConv_PreserveAll, // __attribute__((preserve_all)) ZigClangCallingConv_AArch64VectorCall, // __attribute__((aarch64_vector_pcs)) diff --git a/src/zig_llvm.cpp b/src/zig_llvm.cpp index d0bc24ed1b..83f3be3144 100644 --- a/src/zig_llvm.cpp +++ b/src/zig_llvm.cpp @@ -155,10 +155,6 @@ LLVMTargetMachineRef ZigLLVMCreateTargetMachine(LLVMTargetRef T, const char *Tri TargetOptions opt; - // Work around the missing initialization of this field in the default - // constructor. Use -1 so that the default value is used. - opt.StackProtectorGuardOffset = (unsigned)-1; - opt.FunctionSections = function_sections; switch (float_abi) { case ZigLLVMABITypeDefault: @@ -240,7 +236,7 @@ bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machine_ref, LLVMM if (asm_filename) { std::error_code EC; - dest_asm_ptr = new(std::nothrow) raw_fd_ostream(asm_filename, EC, sys::fs::F_None); + dest_asm_ptr = new(std::nothrow) raw_fd_ostream(asm_filename, EC, sys::fs::OF_None); if (EC) { *error_message = strdup((const char *)StringRef(EC.message()).bytes_begin()); return true; @@ -248,7 +244,7 @@ bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machine_ref, LLVMM } if (bin_filename) { std::error_code EC; - dest_bin_ptr = new(std::nothrow) raw_fd_ostream(bin_filename, EC, sys::fs::F_None); + dest_bin_ptr = new(std::nothrow) raw_fd_ostream(bin_filename, EC, sys::fs::OF_None); if (EC) { *error_message = strdup((const char *)StringRef(EC.message()).bytes_begin()); return true; @@ -256,7 +252,7 @@ bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machine_ref, LLVMM } if (bitcode_filename) { std::error_code EC; - dest_bitcode_ptr = new(std::nothrow) raw_fd_ostream(bitcode_filename, EC, sys::fs::F_None); + dest_bitcode_ptr = new(std::nothrow) raw_fd_ostream(bitcode_filename, EC, sys::fs::OF_None); if (EC) { *error_message = strdup((const char *)StringRef(EC.message()).bytes_begin()); return true; @@ -292,7 +288,7 @@ bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machine_ref, LLVMM StandardInstrumentations std_instrumentations(false); std_instrumentations.registerCallbacks(instr_callbacks); - PassBuilder pass_builder(false, &target_machine, pipeline_opts, + PassBuilder pass_builder(&target_machine, pipeline_opts, None, &instr_callbacks); using OptimizationLevel = typename PassBuilder::OptimizationLevel; @@ -1020,29 +1016,6 @@ void ZigLLVMSetModuleCodeModel(LLVMModuleRef module, LLVMCodeModel code_model) { assert(!JIT); } -static AtomicOrdering mapFromLLVMOrdering(LLVMAtomicOrdering Ordering) { - switch (Ordering) { - case LLVMAtomicOrderingNotAtomic: return AtomicOrdering::NotAtomic; - case LLVMAtomicOrderingUnordered: return AtomicOrdering::Unordered; - case LLVMAtomicOrderingMonotonic: return AtomicOrdering::Monotonic; - case LLVMAtomicOrderingAcquire: return AtomicOrdering::Acquire; - case LLVMAtomicOrderingRelease: return AtomicOrdering::Release; - case LLVMAtomicOrderingAcquireRelease: return AtomicOrdering::AcquireRelease; - case LLVMAtomicOrderingSequentiallyConsistent: return AtomicOrdering::SequentiallyConsistent; - } - abort(); -} - -LLVMValueRef ZigLLVMBuildCmpXchg(LLVMBuilderRef builder, LLVMValueRef ptr, LLVMValueRef cmp, - LLVMValueRef new_val, LLVMAtomicOrdering success_ordering, - LLVMAtomicOrdering failure_ordering, bool is_weak) -{ - AtomicCmpXchgInst *inst = unwrap(builder)->CreateAtomicCmpXchg(unwrap(ptr), unwrap(cmp), - unwrap(new_val), mapFromLLVMOrdering(success_ordering), mapFromLLVMOrdering(failure_ordering)); - inst->setWeak(is_weak); - return wrap(inst); -} - LLVMValueRef ZigLLVMBuildNSWShl(LLVMBuilderRef builder, LLVMValueRef LHS, LLVMValueRef RHS, const char *name) { @@ -1237,38 +1210,6 @@ int ZigLLDLinkWasm(int argc, const char **argv, bool can_exit_early) { return lld::wasm::link(args, can_exit_early, llvm::outs(), llvm::errs()); } -static AtomicRMWInst::BinOp toLLVMRMWBinOp(enum ZigLLVM_AtomicRMWBinOp BinOp) { - switch (BinOp) { - default: - case ZigLLVMAtomicRMWBinOpXchg: return AtomicRMWInst::Xchg; - case ZigLLVMAtomicRMWBinOpAdd: return AtomicRMWInst::Add; - case ZigLLVMAtomicRMWBinOpSub: return AtomicRMWInst::Sub; - case ZigLLVMAtomicRMWBinOpAnd: return AtomicRMWInst::And; - case ZigLLVMAtomicRMWBinOpNand: return AtomicRMWInst::Nand; - case ZigLLVMAtomicRMWBinOpOr: return AtomicRMWInst::Or; - case ZigLLVMAtomicRMWBinOpXor: return AtomicRMWInst::Xor; - case ZigLLVMAtomicRMWBinOpMax: return AtomicRMWInst::Max; - case ZigLLVMAtomicRMWBinOpMin: return AtomicRMWInst::Min; - case ZigLLVMAtomicRMWBinOpUMax: return AtomicRMWInst::UMax; - case ZigLLVMAtomicRMWBinOpUMin: return AtomicRMWInst::UMin; - case ZigLLVMAtomicRMWBinOpFAdd: return AtomicRMWInst::FAdd; - case ZigLLVMAtomicRMWBinOpFSub: return AtomicRMWInst::FSub; - } -} - -static AtomicOrdering toLLVMOrdering(LLVMAtomicOrdering Ordering) { - switch (Ordering) { - default: - case LLVMAtomicOrderingNotAtomic: return AtomicOrdering::NotAtomic; - case LLVMAtomicOrderingUnordered: return AtomicOrdering::Unordered; - case LLVMAtomicOrderingMonotonic: return AtomicOrdering::Monotonic; - case LLVMAtomicOrderingAcquire: return AtomicOrdering::Acquire; - case LLVMAtomicOrderingRelease: return AtomicOrdering::Release; - case LLVMAtomicOrderingAcquireRelease: return AtomicOrdering::AcquireRelease; - case LLVMAtomicOrderingSequentiallyConsistent: return AtomicOrdering::SequentiallyConsistent; - } -} - inline LLVMAttributeRef wrap(Attribute Attr) { return reinterpret_cast(Attr.getRawPointer()); } @@ -1277,16 +1218,6 @@ inline Attribute unwrap(LLVMAttributeRef Attr) { return Attribute::fromRawPointer(Attr); } -LLVMValueRef ZigLLVMBuildAtomicRMW(LLVMBuilderRef B, enum ZigLLVM_AtomicRMWBinOp op, - LLVMValueRef PTR, LLVMValueRef Val, - LLVMAtomicOrdering ordering, LLVMBool singleThread) -{ - AtomicRMWInst::BinOp intop = toLLVMRMWBinOp(op); - return wrap(unwrap(B)->CreateAtomicRMW(intop, unwrap(PTR), - unwrap(Val), toLLVMOrdering(ordering), - singleThread ? SyncScope::SingleThread : SyncScope::System)); -} - LLVMValueRef ZigLLVMBuildAndReduce(LLVMBuilderRef B, LLVMValueRef Val) { return wrap(unwrap(B)->CreateAndReduce(unwrap(Val))); } @@ -1343,6 +1274,7 @@ static_assert((Triple::ArchType)ZigLLVM_bpfel == Triple::bpfel, ""); static_assert((Triple::ArchType)ZigLLVM_bpfeb == Triple::bpfeb, ""); static_assert((Triple::ArchType)ZigLLVM_csky == Triple::csky, ""); static_assert((Triple::ArchType)ZigLLVM_hexagon == Triple::hexagon, ""); +static_assert((Triple::ArchType)ZigLLVM_m68k == Triple::m68k, ""); static_assert((Triple::ArchType)ZigLLVM_mips == Triple::mips, ""); static_assert((Triple::ArchType)ZigLLVM_mipsel == Triple::mipsel, ""); static_assert((Triple::ArchType)ZigLLVM_mips64 == Triple::mips64, ""); @@ -1459,6 +1391,7 @@ static_assert((Triple::EnvironmentType)ZigLLVM_Android == Triple::Android, ""); static_assert((Triple::EnvironmentType)ZigLLVM_Musl == Triple::Musl, ""); static_assert((Triple::EnvironmentType)ZigLLVM_MuslEABI == Triple::MuslEABI, ""); static_assert((Triple::EnvironmentType)ZigLLVM_MuslEABIHF == Triple::MuslEABIHF, ""); +static_assert((Triple::EnvironmentType)ZigLLVM_MuslX32 == Triple::MuslX32, ""); static_assert((Triple::EnvironmentType)ZigLLVM_MSVC == Triple::MSVC, ""); static_assert((Triple::EnvironmentType)ZigLLVM_Itanium == Triple::Itanium, ""); static_assert((Triple::EnvironmentType)ZigLLVM_Cygnus == Triple::Cygnus, ""); diff --git a/src/zig_llvm.h b/src/zig_llvm.h index f49c2662c6..e16da15036 100644 --- a/src/zig_llvm.h +++ b/src/zig_llvm.h @@ -137,10 +137,6 @@ ZIG_EXTERN_C LLVMValueRef ZigLLVMBuildUMin(LLVMBuilderRef builder, LLVMValueRef ZIG_EXTERN_C LLVMValueRef ZigLLVMBuildSMax(LLVMBuilderRef builder, LLVMValueRef LHS, LLVMValueRef RHS, const char* name); ZIG_EXTERN_C LLVMValueRef ZigLLVMBuildSMin(LLVMBuilderRef builder, LLVMValueRef LHS, LLVMValueRef RHS, const char* name); -ZIG_EXTERN_C LLVMValueRef ZigLLVMBuildCmpXchg(LLVMBuilderRef builder, LLVMValueRef ptr, LLVMValueRef cmp, - LLVMValueRef new_val, LLVMAtomicOrdering success_ordering, - LLVMAtomicOrdering failure_ordering, bool is_weak); - ZIG_EXTERN_C LLVMValueRef ZigLLVMBuildNSWShl(LLVMBuilderRef builder, LLVMValueRef LHS, LLVMValueRef RHS, const char *name); ZIG_EXTERN_C LLVMValueRef ZigLLVMBuildNUWShl(LLVMBuilderRef builder, LLVMValueRef LHS, LLVMValueRef RHS, @@ -303,6 +299,7 @@ enum ZigLLVM_ArchType { ZigLLVM_bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian) ZigLLVM_csky, // CSKY: csky ZigLLVM_hexagon, // Hexagon: hexagon + ZigLLVM_m68k, // M68k: Motorola 680x0 family ZigLLVM_mips, // MIPS: mips, mipsallegrex, mipsr6 ZigLLVM_mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el ZigLLVM_mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6 @@ -345,7 +342,6 @@ enum ZigLLVM_ArchType { ZigLLVM_renderscript32, // 32-bit RenderScript ZigLLVM_renderscript64, // 64-bit RenderScript ZigLLVM_ve, // NEC SX-Aurora Vector Engine - ZigLLVM_LastArchType = ZigLLVM_ve }; @@ -430,6 +426,7 @@ enum ZigLLVM_EnvironmentType { ZigLLVM_Musl, ZigLLVM_MuslEABI, ZigLLVM_MuslEABIHF, + ZigLLVM_MuslX32, ZigLLVM_MSVC, ZigLLVM_Itanium, @@ -437,7 +434,6 @@ enum ZigLLVM_EnvironmentType { ZigLLVM_CoreCLR, ZigLLVM_Simulator, // Simulator variants of other systems, e.g., Apple's iOS ZigLLVM_MacABI, // Mac Catalyst variant of Apple's iOS deployment target. - ZigLLVM_LastEnvironmentType = ZigLLVM_MacABI }; @@ -452,26 +448,6 @@ enum ZigLLVM_ObjectFormatType { ZigLLVM_XCOFF, }; -enum ZigLLVM_AtomicRMWBinOp { - ZigLLVMAtomicRMWBinOpXchg, - ZigLLVMAtomicRMWBinOpAdd, - ZigLLVMAtomicRMWBinOpSub, - ZigLLVMAtomicRMWBinOpAnd, - ZigLLVMAtomicRMWBinOpNand, - ZigLLVMAtomicRMWBinOpOr, - ZigLLVMAtomicRMWBinOpXor, - ZigLLVMAtomicRMWBinOpMax, - ZigLLVMAtomicRMWBinOpMin, - ZigLLVMAtomicRMWBinOpUMax, - ZigLLVMAtomicRMWBinOpUMin, - ZigLLVMAtomicRMWBinOpFAdd, - ZigLLVMAtomicRMWBinOpFSub, -}; - -LLVMValueRef ZigLLVMBuildAtomicRMW(LLVMBuilderRef B, enum ZigLLVM_AtomicRMWBinOp op, - LLVMValueRef PTR, LLVMValueRef Val, - LLVMAtomicOrdering ordering, LLVMBool singleThread); - LLVMValueRef ZigLLVMBuildAndReduce(LLVMBuilderRef B, LLVMValueRef Val); LLVMValueRef ZigLLVMBuildOrReduce(LLVMBuilderRef B, LLVMValueRef Val); LLVMValueRef ZigLLVMBuildXorReduce(LLVMBuilderRef B, LLVMValueRef Val); -- cgit v1.2.3 From 303e1a062cdafa0fe06c4a78dabe0a077c239e04 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Wed, 1 Sep 2021 15:38:58 -0700 Subject: re-enable mips behavior tests for vectors closes #3317 --- lib/std/fmt.zig | 4 ---- lib/std/hash/auto_hash.zig | 3 --- test/behavior/byteswap.zig | 3 --- test/behavior/popcount.zig | 3 --- test/behavior/shuffle.zig | 3 +-- 5 files changed, 1 insertion(+), 15 deletions(-) (limited to 'lib/std') diff --git a/lib/std/fmt.zig b/lib/std/fmt.zig index 52bc25af00..402770456e 100644 --- a/lib/std/fmt.zig +++ b/lib/std/fmt.zig @@ -2504,10 +2504,6 @@ test "positional/alignment/width/precision" { } test "vector" { - if (builtin.target.cpu.arch == .mipsel or builtin.target.cpu.arch == .mips) { - // https://github.com/ziglang/zig/issues/3317 - return error.SkipZigTest; - } if (builtin.target.cpu.arch == .riscv64) { // https://github.com/ziglang/zig/issues/4486 return error.SkipZigTest; diff --git a/lib/std/hash/auto_hash.zig b/lib/std/hash/auto_hash.zig index 4f037349ba..0049991378 100644 --- a/lib/std/hash/auto_hash.zig +++ b/lib/std/hash/auto_hash.zig @@ -399,9 +399,6 @@ test "testHash union" { } test "testHash vector" { - // Disabled because of #3317 - if (builtin.target.cpu.arch == .mipsel or builtin.target.cpu.arch == .mips) return error.SkipZigTest; - const a: meta.Vector(4, u32) = [_]u32{ 1, 2, 3, 4 }; const b: meta.Vector(4, u32) = [_]u32{ 1, 2, 3, 5 }; try testing.expect(testHash(a) == testHash(a)); diff --git a/test/behavior/byteswap.zig b/test/behavior/byteswap.zig index 7ec1b5379f..4affc99b59 100644 --- a/test/behavior/byteswap.zig +++ b/test/behavior/byteswap.zig @@ -39,9 +39,6 @@ test "@byteSwap integers" { } test "@byteSwap vectors" { - // https://github.com/ziglang/zig/issues/3317 - if (std.Target.current.cpu.arch == .mipsel or std.Target.current.cpu.arch == .mips) return error.SkipZigTest; - const ByteSwapVectorTest = struct { fn run() !void { try t(u8, 2, [_]u8{ 0x12, 0x13 }, [_]u8{ 0x12, 0x13 }); diff --git a/test/behavior/popcount.zig b/test/behavior/popcount.zig index 0a2352340d..1ee4b33190 100644 --- a/test/behavior/popcount.zig +++ b/test/behavior/popcount.zig @@ -46,9 +46,6 @@ fn testPopCountIntegers() !void { } test "@popCount vectors" { - // https://github.com/ziglang/zig/issues/3317 - if (std.Target.current.cpu.arch == .mipsel or std.Target.current.cpu.arch == .mips) return error.SkipZigTest; - comptime try testPopCountVectors(); try testPopCountVectors(); } diff --git a/test/behavior/shuffle.zig b/test/behavior/shuffle.zig index 3ccfc50f0b..e0f973762e 100644 --- a/test/behavior/shuffle.zig +++ b/test/behavior/shuffle.zig @@ -35,8 +35,7 @@ test "@shuffle" { try expect(mem.eql(i32, &@as([4]i32, res), &[4]i32{ 2147483647, 3, -2, 4 })); // bool - // https://github.com/ziglang/zig/issues/3317 - if (builtin.target.cpu.arch != .mipsel and builtin.target.cpu.arch != .mips) { + { var x2: Vector(4, bool) = [4]bool{ false, true, false, true }; var v4: Vector(2, bool) = [2]bool{ true, false }; const mask5: Vector(4, i32) = [4]i32{ 0, ~@as(i32, 1), 1, 2 }; -- cgit v1.2.3 From 7a2624c3e40e2386a4a8a775b839e1d67608ec42 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Fri, 1 Oct 2021 22:32:13 -0700 Subject: std: disable ArrayBitSet test on aarch64 See #9879. This regressed with the release of LLVM 13.0.0. --- lib/std/bit_set.zig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'lib/std') diff --git a/lib/std/bit_set.zig b/lib/std/bit_set.zig index dd8afb4168..af960784f7 100644 --- a/lib/std/bit_set.zig +++ b/lib/std/bit_set.zig @@ -1167,6 +1167,10 @@ test "IntegerBitSet" { } test "ArrayBitSet" { + if (@import("builtin").cpu.arch == .aarch64) { + // https://github.com/ziglang/zig/issues/9879 + return error.SkipZigTest; + } inline for (.{ 0, 1, 2, 31, 32, 33, 63, 64, 65, 254, 500, 3000 }) |size| { try testStaticBitSet(ArrayBitSet(u8, size)); try testStaticBitSet(ArrayBitSet(u16, size)); -- cgit v1.2.3