From 3d7fb4f204940875e7cd9e4dd82f28c464f688e8 Mon Sep 17 00:00:00 2001
From: Alex Rønne Petersen <alex@alexrp.com>
Date: Mon, 30 Jun 2025 06:59:06 +0200
Subject: std.zig.system.linux: Add detection for some extra RISC-V CPUs

---
 lib/std/zig/system/linux.zig | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'lib/std')

diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig
index a0935bdb05..d8cff2403f 100644
--- a/lib/std/zig/system/linux.zig
+++ b/lib/std/zig/system/linux.zig
@@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {
 
     const cpu_names = .{
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
+        .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {
-- 
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