From dd5929402cebad821285fb6f112f48f8e63a393d Mon Sep 17 00:00:00 2001 From: Joshua Ashton Date: Tue, 19 Sep 2023 10:29:31 -0100 Subject: [PATCH] HACK: Prefix new color mgmt properties with VALVE1_ Plane color mgmt properties, predefined transfer functions and CRTC shaper/3D LUT aren't upstream properties yet, add a prefix to indicate they are downstream props. Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index c87b64e464ed5..0a7df5984d0b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -226,7 +226,7 @@ amdgpu_dm_create_color_properties(struct amdgpu_device *adev) prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, - "AMD_PLANE_DEGAMMA_LUT", 0); + "VALVE1_PLANE_DEGAMMA_LUT", 0); if (!prop) return -ENOMEM; adev->mode_info.plane_degamma_lut_property = prop; @@ -240,41 +240,41 @@ amdgpu_dm_create_color_properties(struct amdgpu_device *adev) adev->mode_info.plane_degamma_lut_size_property = prop; prop = amdgpu_create_tf_property(adev_to_drm(adev), - "AMD_PLANE_DEGAMMA_TF", + "VALVE1_PLANE_DEGAMMA_TF", amdgpu_eotf); if (!prop) return -ENOMEM; adev->mode_info.plane_degamma_tf_property = prop; prop = drm_property_create_range(adev_to_drm(adev), - 0, "AMD_PLANE_HDR_MULT", 0, U64_MAX); + 0, "VALVE1_PLANE_HDR_MULT", 0, U64_MAX); if (!prop) return -ENOMEM; adev->mode_info.plane_hdr_mult_property = prop; prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, - "AMD_PLANE_CTM", 0); + "VALVE1_PLANE_CTM", 0); if (!prop) return -ENOMEM; adev->mode_info.plane_ctm_property = prop; prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, - "AMD_PLANE_SHAPER_LUT", 0); + "VALVE1_PLANE_SHAPER_LUT", 0); if (!prop) return -ENOMEM; adev->mode_info.plane_shaper_lut_property = prop; prop = drm_property_create_range(adev_to_drm(adev), DRM_MODE_PROP_IMMUTABLE, - "AMD_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX); + "VALVE1_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX); if (!prop) return -ENOMEM; adev->mode_info.plane_shaper_lut_size_property = prop; prop = amdgpu_create_tf_property(adev_to_drm(adev), - "AMD_PLANE_SHAPER_TF", + "VALVE1_PLANE_SHAPER_TF", amdgpu_inv_eotf); if (!prop) return -ENOMEM; @@ -282,41 +282,41 @@ amdgpu_dm_create_color_properties(struct amdgpu_device *adev) prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, - "AMD_PLANE_LUT3D", 0); + "VALVE1_PLANE_LUT3D", 0); if (!prop) return -ENOMEM; adev->mode_info.plane_lut3d_property = prop; prop = drm_property_create_range(adev_to_drm(adev), DRM_MODE_PROP_IMMUTABLE, - "AMD_PLANE_LUT3D_SIZE", 0, UINT_MAX); + "VALVE1_PLANE_LUT3D_SIZE", 0, UINT_MAX); if (!prop) return -ENOMEM; adev->mode_info.plane_lut3d_size_property = prop; prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, - "AMD_PLANE_BLEND_LUT", 0); + "VALVE1_PLANE_BLEND_LUT", 0); if (!prop) return -ENOMEM; adev->mode_info.plane_blend_lut_property = prop; prop = drm_property_create_range(adev_to_drm(adev), DRM_MODE_PROP_IMMUTABLE, - "AMD_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX); + "VALVE1_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX); if (!prop) return -ENOMEM; adev->mode_info.plane_blend_lut_size_property = prop; prop = amdgpu_create_tf_property(adev_to_drm(adev), - "AMD_PLANE_BLEND_TF", + "VALVE1_PLANE_BLEND_TF", amdgpu_eotf); if (!prop) return -ENOMEM; adev->mode_info.plane_blend_tf_property = prop; prop = amdgpu_create_tf_property(adev_to_drm(adev), - "AMD_CRTC_REGAMMA_TF", + "VALVE1_CRTC_REGAMMA_TF", amdgpu_inv_eotf); if (!prop) return -ENOMEM; -- GitLab From a5ae6b501aed085d27541c284893e431776fe259 Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Mon, 25 Sep 2023 16:25:27 -0100 Subject: [PATCH] HACK: change TF API to fit current gamescope upstream requested to identify if the type of transfer function a property is capable to handle (basically EOTF or inv_EOTF). gamescope understand it is implictly identified by the block/property position in the pipeline and doesn't handle this difference yet. change the upstream API to fit the current gamescope implementation. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 21 +++--- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 69 ++++++++----------- 2 files changed, 38 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 9c1871b866cc9..feaa82f74a68f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -734,19 +734,14 @@ extern const struct amdgpu_ip_block_version dm_ip_block; */ enum amdgpu_transfer_function { AMDGPU_TRANSFER_FUNCTION_DEFAULT, - AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, - AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, - AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, - AMDGPU_TRANSFER_FUNCTION_IDENTITY, - AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, - AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, - AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, - AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, - AMDGPU_TRANSFER_FUNCTION_BT709_OETF, - AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, - AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, - AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, - AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, + AMDGPU_TRANSFER_FUNCTION_SRGB, + AMDGPU_TRANSFER_FUNCTION_BT709, + AMDGPU_TRANSFER_FUNCTION_PQ, + AMDGPU_TRANSFER_FUNCTION_LINEAR, + AMDGPU_TRANSFER_FUNCTION_UNITY, + AMDGPU_TRANSFER_FUNCTION_GAMMA22, + AMDGPU_TRANSFER_FUNCTION_GAMMA24, + AMDGPU_TRANSFER_FUNCTION_GAMMA26, AMDGPU_TRANSFER_FUNCTION_COUNT }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 0a7df5984d0b8..21e0efc42a34c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -163,36 +163,31 @@ static inline struct fixed31_32 amdgpu_dm_fixpt_from_s3132(__u64 x) static const char * const amdgpu_transfer_function_names[] = { [AMDGPU_TRANSFER_FUNCTION_DEFAULT] = "Default", - [AMDGPU_TRANSFER_FUNCTION_IDENTITY] = "Identity", - [AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF] = "sRGB EOTF", - [AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF] = "BT.709 inv_OETF", - [AMDGPU_TRANSFER_FUNCTION_PQ_EOTF] = "PQ EOTF", - [AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF] = "Gamma 2.2 EOTF", - [AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF] = "Gamma 2.4 EOTF", - [AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF] = "Gamma 2.6 EOTF", - [AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF] = "sRGB inv_EOTF", - [AMDGPU_TRANSFER_FUNCTION_BT709_OETF] = "BT.709 OETF", - [AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF] = "PQ inv_EOTF", - [AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF] = "Gamma 2.2 inv_EOTF", - [AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF] = "Gamma 2.4 inv_EOTF", - [AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF] = "Gamma 2.6 inv_EOTF", + [AMDGPU_TRANSFER_FUNCTION_LINEAR] = "Linear", + [AMDGPU_TRANSFER_FUNCTION_UNITY] = "Unity", + [AMDGPU_TRANSFER_FUNCTION_SRGB] = "sRGB", + [AMDGPU_TRANSFER_FUNCTION_BT709] = "BT.709", + [AMDGPU_TRANSFER_FUNCTION_PQ] = "PQ (Perceptual Quantizer)", + [AMDGPU_TRANSFER_FUNCTION_GAMMA22] = "Gamma 2.2", + [AMDGPU_TRANSFER_FUNCTION_GAMMA24] = "Gamma 2.4", + [AMDGPU_TRANSFER_FUNCTION_GAMMA26] = "Gamma 2.6", }; static const u32 amdgpu_eotf = - BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF) | - BIT(AMDGPU_TRANSFER_FUNCTION_PQ_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF); + BIT(AMDGPU_TRANSFER_FUNCTION_SRGB) | + BIT(AMDGPU_TRANSFER_FUNCTION_BT709) | + BIT(AMDGPU_TRANSFER_FUNCTION_PQ) | + BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22) | + BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24) | + BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26); static const u32 amdgpu_inv_eotf = - BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_BT709_OETF) | - BIT(AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF) | - BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF); + BIT(AMDGPU_TRANSFER_FUNCTION_SRGB) | + BIT(AMDGPU_TRANSFER_FUNCTION_BT709) | + BIT(AMDGPU_TRANSFER_FUNCTION_PQ) | + BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22) | + BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24) | + BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26); static struct drm_property * amdgpu_create_tf_property(struct drm_device *dev, @@ -201,7 +196,8 @@ amdgpu_create_tf_property(struct drm_device *dev, { u32 transfer_functions = supported_tf | BIT(AMDGPU_TRANSFER_FUNCTION_DEFAULT) | - BIT(AMDGPU_TRANSFER_FUNCTION_IDENTITY); + BIT(AMDGPU_TRANSFER_FUNCTION_LINEAR) | + BIT(AMDGPU_TRANSFER_FUNCTION_UNITY); struct drm_prop_enum_list enum_list[AMDGPU_TRANSFER_FUNCTION_COUNT]; int i, len; @@ -645,25 +641,20 @@ amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) switch (tf) { default: case AMDGPU_TRANSFER_FUNCTION_DEFAULT: - case AMDGPU_TRANSFER_FUNCTION_IDENTITY: + case AMDGPU_TRANSFER_FUNCTION_LINEAR: + case AMDGPU_TRANSFER_FUNCTION_UNITY: return TRANSFER_FUNCTION_LINEAR; - case AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF: - case AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF: + case AMDGPU_TRANSFER_FUNCTION_SRGB: return TRANSFER_FUNCTION_SRGB; - case AMDGPU_TRANSFER_FUNCTION_BT709_OETF: - case AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF: + case AMDGPU_TRANSFER_FUNCTION_BT709: return TRANSFER_FUNCTION_BT709; - case AMDGPU_TRANSFER_FUNCTION_PQ_EOTF: - case AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF: + case AMDGPU_TRANSFER_FUNCTION_PQ: return TRANSFER_FUNCTION_PQ; - case AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF: - case AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF: + case AMDGPU_TRANSFER_FUNCTION_GAMMA22: return TRANSFER_FUNCTION_GAMMA22; - case AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF: - case AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF: + case AMDGPU_TRANSFER_FUNCTION_GAMMA24: return TRANSFER_FUNCTION_GAMMA24; - case AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF: - case AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF: + case AMDGPU_TRANSFER_FUNCTION_GAMMA26: return TRANSFER_FUNCTION_GAMMA26; } } -- GitLab From 2f33df4d9d3e86546d7c67453ae799306d55b7f5 Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Sat, 22 Apr 2023 14:08:47 -0100 Subject: [PATCH] HACK: add KConfig to enable driver-specific color mgmt props We are enabling a large set of color calibration features to enhance KMS color mgmt but these properties are specific of AMD display HW, and cannot be provided by other vendors. Therefore, set a config option to enable AMD driver-private properties used on Steam Deck color mgmt pipeline. Replace the agreed name `AMD_PRIVATE_COLOR` with our downstream version `CONFIG_DRM_AMD_COLOR_STEAMDECK`. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/Kconfig | 7 +++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 +++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +++--- 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 901d1961b7392..49523fa82f92a 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -51,4 +51,11 @@ config DRM_AMD_SECURE_DISPLAY This option enables the calculation of crc of specific region via debugfs. Cooperate with specific DMCU FW. +config DRM_AMD_COLOR_STEAMDECK + bool "Enable color calibration features for Steam Deck" + depends on DRM_AMD_DC + help + Choose this option if you want to use AMDGPU features for broader + color management support on Steam Deck. + endmenu diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5853cf0229176..1718ddfe75083 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4074,7 +4074,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) return r; } -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK if (amdgpu_dm_create_color_properties(adev)) return -ENOMEM; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 21e0efc42a34c..8f8d2a8fb2921 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -97,7 +97,7 @@ static inline struct fixed31_32 amdgpu_dm_fixpt_from_s3132(__u64 x) return val; } -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK /* Pre-defined Transfer Functions (TF) * * AMD driver supports pre-defined mathematical functions for transferring diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 6e715ef3a5566..ab9992f24ae21 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -290,7 +290,7 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) } #endif -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK /** * dm_crtc_additional_color_mgmt - enable additional color properties * @crtc: DRM CRTC @@ -372,7 +372,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, #endif @@ -551,7 +551,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK dm_crtc_additional_color_mgmt(&acrtc->base); #endif return 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8a4c40b4c27e4..5d87c24f0461f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1468,7 +1468,7 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, drm_atomic_helper_plane_destroy_state(plane, state); } -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK static void dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, struct drm_plane *plane) @@ -1659,7 +1659,7 @@ static const struct drm_plane_funcs dm_plane_funcs = { .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, .format_mod_supported = amdgpu_dm_plane_format_mod_supported, -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK .atomic_set_property = dm_atomic_plane_set_property, .atomic_get_property = dm_atomic_plane_get_property, #endif @@ -1742,7 +1742,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(plane, &dm_plane_helper_funcs); -#ifdef AMD_PRIVATE_COLOR +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK dm_atomic_plane_attach_color_mgmt_properties(dm, plane); #endif /* Create (reset) the plane state */ -- GitLab From b938468f07222b4faab5ae5cf5391eccd9532bb0 Mon Sep 17 00:00:00 2001 From: Bouke Sybren Haarsma Date: Fri, 15 Dec 2023 11:14:58 +0100 Subject: [PATCH] Don't create color_mgmt_properties on asics < SIENNA_CICHLID --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 2ed20e6e439bb5..65ee8745e96540 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1742,7 +1742,8 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(plane, &dm_plane_helper_funcs); #ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK - dm_atomic_plane_attach_color_mgmt_properties(dm, plane); + if (dm->adev->asic_type >= CHIP_SIENNA_CICHLID) + dm_atomic_plane_attach_color_mgmt_properties(dm, plane); #endif /* Create (reset) the plane state */ if (plane->funcs->reset) -- 2.43.0